METHOD FOR CHECKING AN M OUT OF N CODE

• US 20140230055A1
• Filed: 06/19/2012
• Published: 08/14/2014
• Est. Priority Date: 07/05/2011
• Status: Abandoned Application

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Boehl, Eberhard
• Application Number:
  US14/130,835
• Publication Number:
  US 20140230055A1
• Time in Patent Office: Days
• US Class Current: 726/22
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: H03M 13/51 Constant weight codes; n-out-of-m codes; Berger codes
• CPC Class Codes: H03M 13/618 Shortening and extension of codes
• CPC Class Codes: H04L 2209/04 Masking or blinding
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/004 for fault attacks

Abstract

A method and a circuit system for checking an m out of n code are provided. The method uses a code checker, to which at least one code reducer is assigned, a reduction of the code word width to in each case half being carried out using the at least one code reducer until a 1 out of x (x=n/2, n/4, n/8 . . . ) code or another code which is not reducible further in this way is provided, each step of the code reducer additionally being connected to different bits of a counter, the 1 out of x code or the code which is not further reducible being checked and additionally the signal pairs of each step being checked.

Claims

1-10. -10. (canceled)

11. A method for checking an m out of n code, comprising:

providing at least one code checker;

assigning to the code checker at least one code reducer;

in the at least one code reducer, carrying out a reduction of a code word width to in each case half until one of a 1 out of x (x=n/2, n/4, n/8 . . . ) code and another code which is not reducible further in this way is provided;

connecting each of the at least one code reducer to different bits of a counter;

checking the at least one of the 1 out of x code and the code which is not reducible further; and

checking signal pairs of each of the at least one code reducer.

12. The method as recited in claim 11, wherein the at least one code reducer includes multiple code reducers that are assigned.

13. The method as recited in claim 11, wherein the code check is carried out multiple times for various partial codes.

14. The method as recited in claim 13, wherein different counter states are provided for each partial code check.

15. The method as recited in claim 13, wherein the partial codes are successively checked using the same code checker.

16. The method as recited in claim 13, wherein the partial codes are checked using various code checkers.

17. The method as recited in claim 12, wherein:

at least one of the at least one code reducers includes multiple full adders, in a first code reducer, n/2 full adders are used,

a summation bit of one full adder is led in each case to a transfer input of the next full adder and the n/2 transfer bits of the n/2 full adders are output,

the transfer input of the first full adder is connected to an output of a first counter bit and this signal forms a first signal pair with a summation output of the last full adder.

18. The method as recited in claim 17, wherein:

a second code reducer includes n/4 full adders,

n/2 output bits of a first step are connected to operand inputs of the full adders of the second code reducer,

summation bits of the full adders are each switched to a transfer input of the next full adder and n/4 transfer bits of the n/4 full adders are output,

a second counter bit is switched to a transfer input of the first full adder of a second step and this second counter bit, together with an output summation bit of the last full adder of the second step, form a second signal pair.

19. The method as recited in claim 17, wherein one signal is inverted for each of the signal pairs and thus modified signal pairs are formed.

20. A circuit system for checking an m out of n code, comprising:

a code checker, to which at least one code reducer is assigned, at least one of the at least one code reducers including multiple full adders, wherein;

the first code reducer uses n/2 full adders,

a summation bit of one full adder is led in each case to a transfer input of the next full adder,

n/2 transfer bits of the n/2 full adders are output,

a transfer input of a first full adder is connected to an output of a first counter bit and this signal, with a summation output of the last full adder, form a first signal pair.