SEMICONDUCTOR DEVICE

• US 20140231905A1
• Filed: 07/22/2011
• Published: 08/21/2014
• Est. Priority Date: 07/22/2011
• Status: Active Grant

• Current Assignee: X-FAB Semiconductor Foundries GmbH (X-FAB Silicon Foundries SE)
• Original Assignee: X-FAB Semiconductor Foundries AG (X-FAB Silicon Foundries SE)
• Inventors: Jeong, Yong Hun, Bong, Bui Ngo, Tay, Yen Thing, Manso, Iliyana
• Granted Patent: US 9,496,357 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A trench MOSFET including: an epitaxial layer; a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface; a trench; a trench bottom oxide in the trench; and polysilicon in the trench, the trench bottom oxide and the polysilicon forming a second interface; where the first and second interfaces are substantially aligned or are at substantially the same level.

Claims

1. A trench MOSFET comprising:

an epitaxial layer;

a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface;

a trench;

a trench bottom oxide in the trench; and

polysilicon in the trench, the trench bottom oxide and the polysilicon forming a second interface;

wherein the first and second interfaces are substantially aligned or are at substantially the same level.

2. A trench MOSFET according to claim 1, wherein a laterally outer region of the second interface is at substantially the same level as a region of the first interface.

3. A trench MOSFET according to claim 1, wherein a region of the second interface which is immediately adjacent a sidewall of the trench is at substantially the same level as a region of the first interface.

4. A trench MOSFET according to claim 1, wherein the highest point of the second interface is at substantially the same level as a region of the first interface.

5. A trench MOSFET according to claim 1, wherein there is no overlap between the body region and the trench bottom oxide, or any such overlap is sufficiently small so that a threshold voltage and/or an On-resistance of the MOSFET is substantially not increased, wherein any such increase is no more than 5% when compared with a MOSFET without overlap.

6. A trench MOSFET according to claim 1, wherein the distance between the body region and the trench bottom oxide is less than about 0.2 μ

m.

7. A trench MOSFET according to claim 5, wherein the overlap is an overlap between the body region and the trench bottom oxide along a line defined by the trench side wall.

8. A trench MOSFET according to claim 5, wherein the overlap is less than about 25 nm.

9. A trench MOSFET according to claim 6, wherein the distance is a distance between the body region and the trench bottom oxide along a line defined by the trench side wall.

10. A method of filling a trench of a semiconductor device comprising:

depositing a first material in the trench including the sidewall of the trench so as to form at least one overhang portion, wherein the first material leaves a void in the trench, the void having a first cross sectional area at a first level of the at least one overhang portion, and a second cross sectional area at a second, deeper level in the trench, wherein the first cross sectional area is smaller than the second cross sectional area;

at least partially removing the at least one overhang portion; and

depositing a second material in the trench.

11. A method according to claim 10, wherein the first and second cross sectional areas extend parallel to the surface of the device.

12. A method according to claim 11, wherein depositing the second material in the trench comprises depositing the second material in the void defined by the first material.

13. A method according to claim 12, wherein depositing the second material in the void comprises substantially filling the void.

14. A method according to claim 10, wherein the at least one overhang portion is located at the corners of the trench.

15. A method according to claim 10, wherein at least partially removing the at least one overhang portion comprises substantially fully removing the at least one overhang portion.

16. A method according to claim 10, wherein at least partially removing the at least one overhang portion comprises an etching step.

17. A method according to claim 16, wherein the etching step comprises an anisotropic etching step.

18. A method according to claim 10, wherein the first and second materials are the same.

19. A method according to claim 10, wherein the first and second materials comprise silicon oxide.

20. A method according to claim 10, wherein the semiconductor device comprises a trench MOSFET.

21. A semiconductor device comprising a trench having a convex trench bottom oxide.

22. A semiconductor device according to claim 21, wherein the trench bottom oxide comprises a first trench bottom oxide portion occupying substantially the entire width of the trench, and a second trench bottom oxide portion on the first trench bottom oxide portion, the second trench bottom oxide portion occupying substantially less than the entire width of the trench.

23. A semiconductor device according to claim 22, wherein the second trench bottom oxide portion occupies a central portion of the trench with respect to the width of the trench.

24. A semiconductor device according to claim 22, wherein the second trench bottom oxide portion does not extend to the top of the trench.

25. A semiconductor device according to claim 22, wherein the second trench bottom oxide portion extends to the top of the trench.

26. A method of manufacturing the semiconductor device according to claim 22, comprising:

depositing the first trench bottom oxide portion in the trench;

forming at least one spacer in the trench and on the first trench bottom oxide portion; and

thereafter

depositing the second trench bottom oxide portion in the trench and on the first trench bottom oxide portion.

27. A method according to claim 26, further comprising using the at least one spacer so as to form the second trench bottom oxide portion in a self-aligned manner.

28. A semiconductor device comprising a trench which is substantially completely filled and having a width of less than 0.25 μ

m, wherein a trench bottom oxide is located in the trench.

29. A semiconductor device according to claim 28, wherein the width of the trench is less than about 0.2 μ

m.