METHODS AND SYSTEMS TO STRESS-PROGRAM AN INTEGRATED CIRCUIT
First Claim
1. An apparatus, comprising:
- a first integrated circuit block to assert complementary logic states at outputs of the first IC block based on complementary logic states at inputs of the first IC block;
wherein the first IC block is stressed while complimentary logic states are applied to the inputs, to program the first IC block to assert pre-determined complementary logic states at the outputs upon de-activation of a reset control without assertion of the complementary logic states at the inputs.
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Accused Products
Abstract
Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program, the first block is configured with first-block program parameters to cause the first block to output a pre-determined value. The first block is stressed while configured with the first-block program parameters, to cause the first block to output the pre-determined value without the first-block program parameters. The first block may include a latch designed as a fully balance circuit and may be asymmetrically stressed to alter a characteristic of one path relative to another. The pre-determined value may be selected to compensate for process corner variations and/or other random variations.
10 Citations
28 Claims
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1. An apparatus, comprising:
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a first integrated circuit block to assert complementary logic states at outputs of the first IC block based on complementary logic states at inputs of the first IC block; wherein the first IC block is stressed while complimentary logic states are applied to the inputs, to program the first IC block to assert pre-determined complementary logic states at the outputs upon de-activation of a reset control without assertion of the complementary logic states at the inputs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method, comprising:
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asserting complementary logic states at inputs of a first integrated circuit (IC) block to cause the first IC block to assert pre-determined complementary logic states at outputs of the first IC block; and stressing at least a portion of the first IC block while the complementary logic states are asserted at the inputs, to program the first IC block to assert the pre-determined complementary logic states upon de-activation of a reset control without assertion of the complementary logic states at the inputs. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A non-transitory computer readable medium encoded with a computer program, including instructions to cause a processor to:
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provide complementary logic states to inputs of a first integrated circuit (IC) block to cause the first IC block to assert pre-determined complementary logic states at outputs of the first IC block; and control a system to stress at least a portion of the first IC block while the complementary logic states are asserted at the inputs, to program the first IC block to assert the pre-determined complementary logic states at the outputs upon de-activation of a reset control without assertion of the complementary logic states at the inputs. - View Dependent Claims (21, 22)
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23. The computer readable medium of claim 23, wherein the first IC block and a second IC block are on a same IC die, and wherein the computer readable medium further includes instructions to cause the processor to:
configure the first IC block to provide at least one of the pre-determined complementary logic states to the second IC block as a pre-determined compensation value to compensate for one or more of process corner variations and random variations imparted by one or more IC blocks of the IC die. - View Dependent Claims (24)
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25. A system, comprising an integrated circuit (IC) die, including:
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a processor and memory; and compensation circuitry, including a stress-programmable configuration register to assert a pre-determined configuration register value following a reset to compensate for one or more of process corner variations and random variations imparted by one or more IC blocks of the IC die. - View Dependent Claims (26, 27, 28)
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Specification