ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY COMPRISING THE SAME, AND METHOD FOR MANUFACTURING THE SAME

• US 20140232685A1
• Filed: 04/28/2014
• Published: 08/21/2014
• Est. Priority Date: 09/05/2008
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: WANG, ZHENG, RYU, JAI-IL
• Granted Patent: US 9,557,864 B2
• Time in Patent Office: Days
• US Class Current: 345/174
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0447 Position sensing using the local deformation of sensor cells
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

The present invention provides an array substrate, a liquid crystal display device comprising the same, and a method for forming the same. The array substrate comprises a gate line, a data line, a signal line and a pixel electrode formed thereon. The gate line intersects the data line to define a plurality of pixel regions in which the pixel electrodes are formed. Each of the pixel electrodes overlaps the signal line to form a first sensing capacitor and overlaps the gate line to form a second sensing capacitor.

Claims

1. An array substrate for a liquid crystal display device, comprising a gate line, a data line, a signal line and a pixel electrode formed thereon, the gate line intersecting the data line to define a pixel region in which the pixel electrode is formed,

wherein the signal line is parallel with the data line, the pixel electrode overlaps the signal line to form a first sensing capacitor and overlaps one gate line to form a second sensing capacitor.

2. The array substrate of claim 1, wherein the data line is disposed at one side of the pixel region, and the signal line is disposed at another side of the pixel region opposite to the data line.

3. The array substrate of claim 1, wherein the signal line and the data line are formed of a same material in a same layer.

4. The array substrate of claim 1, wherein the signal line are connected with a narrow timing pulse generator.

5. The array substrate of claim 4, wherein the data line is disposed at one side of the pixel region, and the signal line is disposed at another side of the pixel region opposite to the data line.

6. The array substrate of claim 4, wherein the signal line and the data line are formed of a same material in a same layer.

7. A method for manufacturing an array substrate, comprising:

forming a gate line and a data line on a base substrate, the gate line intersecting the data line to define a pixel region;

forming a signal line parallel with the data line; and

forming a pixel electrode in the pixel region,

wherein the pixel electrode overlaps one signal line to form a first sensing capacitor and overlaps one gate line to form a second sensing capacitor.