Display Circuitry with Reduced Pixel Parasitic Capacitor Coupling

• US 20140232955A1
• Filed: 02/06/2014
• Published: 08/21/2014
• Est. Priority Date: 02/20/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Chang, Shih-Chang, Chang, Ting-Kuo, Yu, Cheng-Ho, Roudbari, Abbas Jamshidi
• Granted Patent: US 9,965,063 B2
• Time in Patent Office: Days
• US Class Current: 349/12
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G06F 3/041 Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes

Abstract

A touch screen display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. Each display pixel in the TFT layer may include first and second TFTs coupled in series between a data line and a storage capacitor. The first TFT may have a gate that is coupled to a gate line. The second TFT may have a gate that is coupled to a control line that is different than the gate line. A global enable signal may be provided on the control line, where the enable signal is asserted during display intervals and is deasserted during touch intervals. The second TFT may be formed using a top-gate TFT or a bottom-gate TFT arrangement.

Claims

1. An electronic device display pixel, comprising:

a data line;

a pixel storage node;

a first control line on which a first control signal is provided;

a second control line on which a second control signal that is different than the first control signal is provided; and

first and second transistors coupled in series between the data line and the pixel storage node, wherein the first transistor has a gate terminal that receives the first control signal from the first control line, and wherein the second transistor has a gate terminal that receives the second control signal from the second control line.

2. The electronic device display pixel defined in claim 1, wherein at least one of the first and second transistors comprises a bottom-gate thin-film transistor.

3. The electronic device display pixel defined in claim 1, wherein the first transistor comprises a top-gate thin-film transistor, and wherein the second transistor comprises a bottom-gate thin-film transistor.

4. The electronic device display pixel defined in claim 1, wherein the first and second transistors comprise top-gate thin-film transistors.

5. The electronic device display pixel defined in claim 1, further comprising:

a third transistor stacked in series with the first transistor, wherein the third transistor has a gate that receives the first control signal from the first control line.

6. The electronic device display pixel defined in claim 5, wherein the third transistor comprises a top-gate thin-film transistor.

7. The electronic device display pixel defined in claim 1, further comprising:

a common electrode; and

a storage capacitor having a first terminal that is coupled to the pixel storage node and a second terminal that is coupled to the common electrode.

8. The electronic device display pixel defined in claim 1, wherein the first and second control lines are formed in different thin-film transistor dielectric layers.

9. The electronic device display pixel defined in claim 1, further comprising:

an electrically floating light shield structure formed below the first transistor.

10. The electronic device display pixel defined in claim 9, further comprising:

an electrically floating conductive member formed above the second transistor.

11. The electronic device display pixel defined in claim 1, wherein the data line is parallel to the second control line and is formed over the second control line.

12. A method of operating an electronic device display pixel that includes a storage capacitor and first and second transistors that are coupled in series between the storage capacitor and a data line, the method comprising:

storing a first pixel value with the storage capacitor;

providing a second pixel value on the data line;

receiving a gate line signal at a gate terminal of the first transistor;

receiving an enable signal at a gate terminal of the second transistor; and

loading the second pixel value into the storage capacitor by asserting the gate line signal and the enable signal.

13. The method defined in claim 12, further comprising:

conveying the gate line signal to the gate terminal of the first transistor via a gate line; and

conveying the enable signal to the gate terminal of the second transistor via a control line that is different than the gate line.

14. The method defined in claim 12, wherein asserting the gate line signal and the enable signal comprises asserting the gate line signal for a first duration and asserting the enable signal for a second duration that is greater than the first duration.

15. The method defined in claim 12, wherein the storage capacitor is coupled to a common electrode, the method further comprising:

driving the common electrode to a constant value during a display mode; and

driving the common electrode to a different value during a touch sensing mode.

16. An electronic device display, comprising:

a control path on which a control signal is provided; and

a plurality of display pixels arranged in rows and columns, wherein each of the display pixels includes first and second transistors coupled in series, wherein the second transistor in each display pixel in a first column of the display pixels is coupled to the control path via a first active circuit, and wherein the second transistor in each display pixel in a second column of the display pixels is coupled to the control path via a second active circuit.

17. The electronic device display defined in claim 16, wherein the first and second active circuits comprise inverting circuits formed using thin-film transistors.

18. The electronic device display defined in claim 16, wherein the first and second active circuits each comprise a first pass transistor that passes a positive power supply voltage and a second pass transistor that passes a ground power supply voltage.

19. The electronic device display defined in claim 16, wherein the second transistor in each display pixel in a third column of the display pixels is coupled to the control path via the first active circuit.

20. The electronic device display defined in claim 16, further comprising:

a gate line on which a gate line signal is provided, wherein the first transistor in at least one display pixel in the first column of the display pixels receives the gate line signal from the gate line, wherein the first transistor in at least one display pixel in the second column of the display pixels receives the gate line signal from the gate line, and wherein the gate line is orthogonal to the control line.