WRITE ASSIST CIRCUIT, MEMORY DEVICE AND METHOD
First Claim
1. A write assist circuit, comprising:
- a first switch coupled between a cell supply voltage node of a memory cell and a power supply voltage node, the first switch configured toconnect the cell supply voltage node to the power supply voltage node for applying a power supply voltage on the power supply voltage node to the memory cell in response to a write control signal having a first state, anddisconnect the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state,a bias voltage circuit configured to generate, at an output thereof, an adjustable bias voltage lower than the power supply voltage; and
a second switch coupled between the cell supply voltage node and the output of the bias voltage circuit, the second switch configured toconnect the cell supply voltage node to the output of the bias voltage circuit for applying the adjustable bias voltage lower than the power supply voltage to the memory cell in response to the write control signal having the second state, anddisconnect the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state.
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Abstract
A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state.
148 Citations
20 Claims
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1. A write assist circuit, comprising:
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a first switch coupled between a cell supply voltage node of a memory cell and a power supply voltage node, the first switch configured to connect the cell supply voltage node to the power supply voltage node for applying a power supply voltage on the power supply voltage node to the memory cell in response to a write control signal having a first state, and disconnect the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state, a bias voltage circuit configured to generate, at an output thereof, an adjustable bias voltage lower than the power supply voltage; and a second switch coupled between the cell supply voltage node and the output of the bias voltage circuit, the second switch configured to connect the cell supply voltage node to the output of the bias voltage circuit for applying the adjustable bias voltage lower than the power supply voltage to the memory cell in response to the write control signal having the second state, and disconnect the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory device, comprising:
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a memory array comprising; a plurality of memory cells arranged in a plurality of columns, and a plurality of cell supply voltage rails each coupled to the memory cells in one of the columns; and a write assist circuit comprising; a bias voltage circuit common to the columns in the memory array and configured to generate, at an output thereof, an adjustable bias voltage, and a plurality of supply voltage switching circuits each corresponding to one of the columns of the memory array and configured to connect the cell supply voltage rail of the corresponding column to the output of the bias voltage circuit in response to the column selected for writing, and connect the cell supply voltage rail of the corresponding column to a power supply voltage node having a power supply voltage higher than the bias voltage in response to the column not selected for writing. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A write assist method, comprising:
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selecting one or more columns among a plurality of columns of a memory device for a write operation; connecting cell supply voltage nodes of memory cells of one or more unselected columns among the columns of the memory device to a power supply voltage node to apply a power supply voltage on the power supply voltage node to the cell supply voltage nodes of the memory cells of the one or more unselected columns; and connecting cell supply voltage nodes of memory cells of the one or more selected columns to an output of a bias voltage circuit shared by the columns in the memory device to apply an adjustable bias voltage at the output of the bias voltage circuit to the cell supply voltage nodes of the memory cells of the one or more selected columns, the adjustable bias voltage lower than the power supply voltage. - View Dependent Claims (20)
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Specification