PACKET PROCESSING WITH REDUCED LATENCY

• US 20140233583A1
• Filed: 02/21/2013
• Published: 08/21/2014
• Est. Priority Date: 02/21/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Anil Vasudevan, Eliezer Tamir, Jesse C. Brandeburg
• Inventors: TAMIR, ELIEZER, BRANDEBURG, JESSE C., VASUDEVAN, ANIL
• Granted Patent: US 10,158,585 B2
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/4498 Finite state machines
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

Claims

1. A driver circuit for reduced latency processing, said driver circuit comprising:

a network stack circuit configured to;

transition from an idle state to a polling state in response to receiving an interrupt from a network interface;

process data from a data queue associated with said network interface, said processing in response to obtaining a queue lock associated with said data queue; and

enable interrupts on said network interface, and return to said idle state in response to determining absence of a yield on said queue lock; and

a queue lock circuit configured to;

provide said queue lock to a first requesting entity if said queue lock is available, wherein said requesting entity comprises said driver circuit and one or more user context processing modules;

record said yield on said queue lock if said queue lock is unavailable in response to a request from a second requesting entity; and

set said network stack circuit to said polling state in response to a release of said queue lock by said first requesting entity and the recording of said yield on said queue lock.

2. The driver circuit of claim 1, wherein said network stack circuit is a network stack state machine and said queue lock circuit is a queue lock state machine.

3. The driver circuit of claim 1, wherein said yield comprises executing a monitor instruction and an mwait instruction on a processor associated with said driver circuit, said monitor and mwait instructions configured to transition said processor to a sleep state, said sleep state terminating in response to availability of data in said data queue.

4. The driver circuit of claim 1, wherein said processing of data by said network stack circuit further comprises providing said data to one of said user context processing modules.

5. The driver circuit of claim 1, further comprising an application programming interface (API) configured to provide access, by said user context processing modules, to said data queue associated with said network interface.

6. The driver circuit of claim 5, wherein said API is further configured to provide access, to an interrupt control register associated with said network interface, said interrupt control register configured to enable postponement of a pending interrupt.

7. The driver circuit of claim 1, wherein said network stack circuit is further configured to disable interrupts from said network interface when transitioning from said idle state to said polling state.

8. The driver circuit of claim 1, wherein said data queue comprises a transmit queue and a receive queue.

9. A network interface for reduced latency processing, said network interface comprising:

a data queue configured to store data descriptors associated with data packets, said data packets transferred between a network and a driver circuit;

an interrupt generation circuit configured to generate an interrupt to said driver circuit, wherein said interrupt is generated based at least in part on at least one of an expiration of a delay timer and a non-empty condition of said data queue; and

an interrupt delay register configured to enable said driver circuit to reset said delay timer, said reset postponing said interrupt generation.

10. The network interface of claim 9, wherein said interrupt is generated in response to a combination of said expiration of said delay timer and said non-empty condition of said data queue.

11. The network interface of claim 9, further comprising a queue fill status circuit configured to indicate said non-empty condition based on a comparison of pointer registers associated with free sections of said data queue and in-use sections of said data queue.

12. A method for reduced latency processing, said method comprising:

transitioning a network stack circuit from an idle state to a polling state in response to receiving an interrupt from a network interface;

processing data from a data queue associated with said network interface, said processing performed by said network stack circuit in response to obtaining a queue lock associated with said data queue;

enabling interrupts on said network interface, and returning said network stack circuit to said idle state in response to determining absence of a yield on said queue lock;

providing said queue lock to a first requesting entity if said queue lock is available, wherein said requesting entity comprises a driver circuit and one or more user context processing modules;

recording said yield on said queue lock if said queue lock is unavailable in response to a request from a second requesting entity; and

setting said network stack circuit to said polling state in response to a release of said queue lock by said first requesting entity and the recording of said yield on said queue lock.

13. The method of claim 12, wherein said network stack circuit is a network stack state machine.

14. The method of claim 12, wherein said yield comprises executing a monitor instruction and an mwait instruction on a processor associated with said driver circuit, said monitor and mwait instructions configured to transition said processor to a sleep state, said sleep state terminating in response to availability of data in said data queue.

15. The method of claim 12, wherein said processing of data by said network stack circuit further comprises providing said data to one of said user context processing modules.

16. The method of claim 12, further comprising providing access, by said user context processing modules, to said data queue associated with said network interface.

17. The method of claim 12, further comprising providing access, by said user context processing modules, to an interrupt control register associated with said network interface, said interrupt control register configured to enable postponement of a pending interrupt.

18. The method of claim 12, further comprising disabling interrupts from said network interface when transitioning said network stack circuit from said idle state to said polling state.

19. A computer-readable storage medium having instructions stored thereon which when executed by a processor result in the following operations for reduced latency processing, said operations comprising:

transitioning a network stack circuit from an idle state to a polling state in response to receiving an interrupt from a network interface;

processing data from a data queue associated with said network interface, said processing performed by said network stack circuit in response to obtaining a queue lock associated with said data queue;

enabling interrupts on said network interface, and returning said network stack circuit to said idle state in response to determining absence of a yield on said queue lock;

providing said queue lock to a first requesting entity if said queue lock is available, wherein said requesting entity comprises a driver circuit and one or more user context processing modules;

recording said yield on said queue lock if said queue lock is unavailable in response to a request from a second requesting entity; and

setting said network stack circuit to said polling state in response to a release of said queue lock by said first requesting entity and the recording of said yield on said queue lock.

20. The computer-readable storage medium of claim 19, wherein said network stack circuit is a network stack state machine.

21. The computer-readable storage medium of claim 19, wherein said yield comprises executing a monitor instruction and an mwait instruction on a processor associated with said driver circuit, said monitor and mwait instructions configured to transition said processor to a sleep state, said sleep state terminating in response to availability of data in said data queue.

22. The computer-readable storage medium of claim 19, wherein said processing of data by said network stack circuit further comprises the operation of providing said data to one of said user context processing modules.

23. The computer-readable storage medium of claim 19, further comprising the operation of providing access, by said user context processing modules, to said data queue associated with said network interface.

24. The computer-readable storage medium of claim 19, further comprising the operation of providing access, by said user context processing modules, to an interrupt control register associated with said network interface, said interrupt control register configured to enable postponement of a pending interrupt.

25. The computer-readable storage medium of claim 19, further comprising the operation of disabling interrupts from said network interface when transitioning said network stack circuit from said idle state to said polling state.