DOUBLE GATE ION SENSITIVE FIELD EFFECT TRANSISTOR

• US 20140234981A1
• Filed: 09/28/2012
• Published: 08/21/2014
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Zarkesh-Ha, Payman, Brueck, Steven R.J., Edwards, Jeremy
• Granted Patent: US 11,008,611 B2
• Time in Patent Office: Days
• US Class Current: 436/94
• CPC Class Codes: C12Q 1/6806 Preparing nucleic acids for analysis, e.g. for polymerase chain reaction [PCR] assay C12Q1/6804 takes precedence
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: C12Q 1/6874 involving nucleic acid arrays, e.g. sequencing by hybridisation
• CPC Class Codes: C12Q 2531/125 Rolling circle
• CPC Class Codes: C12Q 2535/122 Massive parallel sequencing
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: Y10T 436/143333 Saccharide [e.g., DNA, etc.]

Abstract

Devices that include a substrate; a source region and a drain region formed within the substrate and having a channel region provided therebetween; a first insulating layer formed over the channel region; a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material; and a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate.

Claims

1. A device comprising:

a substrate;

a source region and a drain region formed within the substrate and having a channel region provided therebetween;

a first insulating layer formed over the channel region;

a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material;

a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate.

2. The device according to claim 1, wherein the second gate is connected to a control voltage, V_CTRL.

3. The device according to claim 2, wherein when V_CTRL is about 0 V, current can flow through the channel region between the source and the drain.

4. The device according to claim 2, wherein when V_CTRL is greater than about 0 V, less current can flow through the channel region between the source and the drain than when V_CTRL is about 0 V.

5. The device according to claim 2, wherein when V_CTRL is about 5 V or greater, current cannot flow through the channel region between the source and the drain.

6. The device according to claim 1, wherein the analyte in the target material is protons.

7. The device according to claim 1, wherein the device need not be connected to a separate access transistor.

8. The device according to claim 1 further comprising a well positioned over the first floating gate structure, wherein the well is configured to contain the target material.

9. The device according to claim 8, wherein the well has a width that is less than a few microns.

10. An array comprising a plurality of devices according to claim 8, wherein the distance between the center of a well and an adjacent well is less than about a few microns.

11. The array according to claim 10 further comprising electronics configured to monitor current flowing through the channel of each device.

12. The array according to claim 10 further comprising multiple parallel readout circuits.

13. A method of determining the concentration of an analyte in a target material, the method comprising the steps of:

providing a device, the device comprising;

a substrate;

a source region and a drain region formed within the substrate and having a channel region provided therebetween;

a first insulating layer formed over the channel region;

a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material;

a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate;

applying a potential of about 0 V to the second gate;

monitoring the current flowing through the channel region between the source and the drain; and

determining the concentration of the analyte in the target material based on the monitored current.

14. The method according to claim 13 further comprising applying a potential of greater than about 0 V to the second gate in order to stop current flowing through the channel region between the source and the drain.

15. The method according to claim 13 further comprising converting the concentration of the analyte in the target material into a pH measurement.

16. The method according to claim 13 further comprising applying a potential to the source and drain, wherein this potential controls the amount of current flowing through the channel region between the source and the drain in response to the concentration of the analyte in the target material.

17. The method according to claim 16, wherein the potential applied to the source and drain is at least about 5 V.

18. The method according to claim 17, wherein the potential applied to the source and drain of the device causes the device to function in avalanche mode.

19. The method according to claim 17, wherein the current through the channel region is monitored until it can be detected.

20. The method according to claim 19, wherein once the current is detected, the potential applied to the source and the drain is reduced.

21. An array comprising:

a plurality of devices, each of the plurality of devices comprising;

a substrate;

a source region and a drain region formed within the substrate and having a channel region provided therebetween;

a first insulating layer formed over the channel region;

a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material; and

a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate; and

at least one readout circuit, the readout circuit configured to monitor current flowing through the channel region between the source and the drain in at least one of the plurality of devices.

22. The array according to claim 21, wherein the array further comprises a plurality of readout circuits.

23. The array according to claim 22, wherein the array comprises at least about 50 readout circuits.