Method of Semiconductor Integrated Circuit Fabrication

• US 20140235050A1
• Filed: 04/30/2014
• Published: 08/21/2014
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Ching-Fu, Lee, Hsiang-Huan, Wu, Hsien-Chang, Peng, Chao-Hsian
• Granted Patent: US 9,054,161 B2
• Time in Patent Office: Days
• US Class Current: 438/622
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs

Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Claims

1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

providing a substrate;

depositing a conductive layer on the substrate;

forming a patterned hard mask on the conductive layer;

forming a catalyst layer on the conductive layer in a vertical interconnection region;

growing a plurality of carbon nanotubes (CNTs) from the catalyst layer; and

p1 etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

2. The method of claim 1, wherein the patterned hard mask includes one or more carbon-containing materials from the group consisting of graphite, charcoal and halocarbon polymer.

3. The method of claim 1, wherein the catalyst layer includes one or more materials from the group consisting of iron (Fe), cobalt (Co), nickel (Ni) and molybdenum (Mo).

4. The method of claim 1, wherein the catalyst layer is deposited by chemical vapor deposition (CVD).

5. The method of claim 1, wherein the CNTs are grown from the local metal catalyst layer by one or more processes from the group consisting of CVD, arc discharge and laser ablation.

6. The method of claim 1, wherein the metal features are formed simultaneously by etching the conductive layer.

7. The method of claim 6, wherein the metal features are formed by etching the conductive layer using the patterned hard mask as etching mask.

8. The method of claim 6, wherein the metal feature in the vertical interconnection region is formed by etching the conductive layer using the CNTs as etching mask.

9. The method of claim 1, wherein the conductive layer includes aluminium (Al).

10. The method of claim 1, wherein the patterned hard mask includes one or more materials from the group consisting of titanium nitride (TiN), titanium silicon nitride (TiSiN) and silicon oxide.

11. The method of claim 1, further comprising:

depositing an inter level dielectric (ILD) layer between the metal features by high temperature CVD.

12. The method of claim 11, further comprising:

performing a chemical mechanical polishing (CMP) to polish back the ILD layer to expose a top surface of the CNTs.

13. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

providing a substrate having a conductive feature;

depositing a conductive layer on the substrate;

depositing a carbon-containing hard mask on the conductive layer;

patterning the carbon-containing hard mask;

coating a photoresist on the patterned carbon-containing hard mask and the conductive layer;

patterning the photoresist to have an opening to expose at least a portion of the conductive layer such that the portion aligns to the conductive feature on the substrate;

depositing a catalyst layer on the conductive layer in the photoresist opening;

removing the patterned photoresist;

after removing the patterned photoresist, growing a plurality of carbon nanotubes (CNTs) from the catalyst layer;

etching the conductive layer by using the CNTs and the patterned hard mask as etching mask to form metal features; and

depositing an inter-level dielectric (ILD) layer between metal features on the substrate.

14. The method of claim 13, wherein the carbon-containing hard mask includes one or more carbon-containing materials from the group consisting of graphite, charcoal and halocarbon polymer.

15. The method of claim 13, wherein the CNTs is grown from the catalyst layer by chemical vapor deposition (CVD).

16. The method of claim 13, wherein the conductive layer is etched by using the CNTs as an etching mask for the metal feature in a region defined by the patterned carbon-containing hard mask.

17. The method of claim 13, wherein the ILD layer is deposited by CVD utilizing a fairly high temperature.

18. The method of claim 17, wherein during high temperature CVD process, a portion of carbon in the carbon-containing hard mask dissolves into Al layer to form aluminum-carbon (Al—

C) alloy.

19. The method of claim 13, further comprising:

performing a chemical mechanical polishing (CMP) to polish back the excessive ILD layer to expose the top surface of the CNTs.

20. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

providing a substrate;

depositing a conductive layer on the substrate;

forming a patterned hard mask on the conductive layer to define a first region;

forming a patterned photoresist layer on the conductive layer to define a second region;

forming a catalyst layer on the conductive layer in the first and second regions;

growing a plurality of carbon nanotubes (CNTs) from the catalyst layer; and

etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.