REDUCING WRITES TO SOLID STATE DRIVE CACHE MEMORIES OF STORAGE CONTROLLERS

• US 20140237163A1
• Filed: 02/19/2013
• Published: 08/21/2014
• Est. Priority Date: 02/19/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Maharana, Parag R.
• Granted Patent: US 9,189,409 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 2212/222 Non-volatile memory

Abstract

Methods and structure are provided for reducing the number of writes to a cache of a storage controller. One exemplary embodiment includes a storage controller that has a non-volatile flash cache memory, a primary memory that is distinct from the cache memory, and a memory manager. The memory manager is able to receive data for storage in the cache memory, to generate a hash key from the received data, and to compare the hash key to hash values for entries in the cache memory. The memory manager can write the received data to the cache memory if the hash key does not match one of the hash values. Also, the memory manager can modify the primary memory instead of writing to the cache if the hash key matches a hash value, in order to reduce the amount of data written to the cache memory.

Claims

1. A storage controller comprising:

a non-volatile flash cache memory;

a primary memory that is distinct from the cache memory; and

a memory manager operable to receive data for storage in the cache memory, to generate a hash key from the received data, to compare the hash key to hash values for entries in the cache memory, to write the received data to the cache memory if the hash key does not match one of the hash values, and to modify the primary memory instead of writing to the cache if the hash key matches a hash value in order to reduce the amount of data written to the cache memory.

2. The storage controller of claim 1, wherein:

the memory manager is further operable to modify the primary memory by generating a pointer that refers to a cache entry that corresponds with the matching hash value.

3. The storage controller of claim 2, wherein:

the memory manager is further operable to determine a number of pointers in the primary memory that refer to an existing cache entry, and to prevent the modification of the existing cache entry if there are multiple pointers in the primary memory that refer to the existing cache entry.

4. The storage controller of claim 2, wherein:

the cache memory includes an entry that stores data for an address of a logical volume, and

the memory manager is further operable to receive new data that will overwrite the address, to determine that a pointer in the primary memory refers to the cache entry that stores the data that will be overwritten, to generate a new cache entry corresponding to the new data, and to modify the primary memory to include a pointer to the new entry in cache memory.

5. The storage controller of claim 1, wherein:

the hash key and the hash values are generated by a hashing algorithm that maps each unique input to a different value.

6. The storage controller of claim 1, wherein:

the hash key and hash values are generated by a hashing algorithm that does not map each unique input to a different value, and

the memory manager is further operable, responsive to determining that the hash key matches a hash value, to confirm that the received data matches data from the cache entry that corresponds with the matching hash value.

7. The storage controller of claim 1, wherein:

the primary memory comprises a Random Access Memory (RAM).

8. A method comprising:

receiving, at a storage controller, data for storage in a non-volatile flash cache memory of the storage controller;

generating a hash key from the received data, via a memory manager of the storage controller;

comparing the hash key to hash values for entries in the cache;

writing the data to the cache if the hash key does not match one of the hash values; and

modifying a primary memory of the storage controller that is distinct from the cache memory, instead of writing to the cache, if the hash key matches a hash value.

9. The method of claim 8, further comprising:

modifying the primary memory by generating a pointer that refers to a cache entry that corresponds with the matching hash value.

10. The method of claim 9, further comprising:

determining a number of pointers in the primary memory that refer to an existing cache entry; and

preventing the modification of the existing cache entry if there are multiple pointers in the primary memory that refer to the existing cache entry.

11. The method of claim 9, wherein:

the cache memory includes an entry that stores data for an address of a logical volume, and the method further comprises;

receiving new data that will overwrite the address;

determining that a pointer in the primary memory refers to the cache entry that stores the data that will be overwritten;

generating a new cache entry corresponding to the new data; and

modifying the primary memory to include a pointer to the new entry in cache memory.

12. The method of claim 8, further comprising:

generating the hash key and the hash values with a hashing algorithm that maps each unique input to a different value.

13. The method of claim 8, wherein:

the hash key and hash values are generated by a hashing algorithm that does not map each unique input to a different value, and the method further comprises;

confirming, responsive to determining that the hash key matches a hash value, that the received data matches data from the cache entry that corresponds with the matching hash value.

14. The method of claim 8, wherein:

the primary memory comprises a Random Access Memory (RAM).

15. A non-transitory computer readable medium embodying programmed instructions which, when executed by a processor, are operable for performing a method of operating a storage controller, the method comprising:

receiving, at the storage controller, data for storage in a non-volatile flash cache memory of the storage controller;

generating a hash key from the received data, via a memory manager of the storage controller;

comparing the hash key to hash values for entries in the cache;

writing the data to the cache if the hash key does not match one of the hash values; and

modifying a primary memory of the storage controller that is distinct from the cache memory, instead of writing to the cache, if the hash key matches a hash value.

16. The medium of claim 15, the method further comprising:

modifying the primary memory by generating a pointer that refers to a cache entry that corresponds with the matching hash value.

17. The medium of claim 16, the method further comprising:

determining a number of pointers in the primary memory that refer to an existing cache entry; and

preventing the modification of the existing cache entry if there are multiple pointers in the primary memory that refer to the existing cache entry.

18. The medium of claim 16, wherein:

the cache memory includes an entry that stores data for an address of a logical volume, and the method further comprises;

receiving new data that will overwrite the address;

determining that a pointer in the primary memory refers to the cache entry that stores the data that will be overwritten;

generating a new cache entry corresponding to the new data; and

modifying the primary memory to include a pointer to the new entry in cache memory.

19. The method of claim 15, the method further comprising:

generating the hash key and the hash values with a hashing algorithm that maps each unique input to a different value.

20. The medium of claim 15, wherein:

the hash key and hash values are generated by a hashing algorithm that does not map each unique input to a different value, and the method further comprises;

confirming, responsive to determining that the hash key matches a hash value, that the received data matches data from the cache entry that corresponds with the matching hash value.