Mass Storage Controller Volatile Memory Containing Metadata Related to Flash Memory Storage

• US 20140237168A1
• Filed: 04/25/2014
• Published: 08/21/2014
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Prins, Douglas A., Olbrich, Aaron K.
• Granted Patent: US 9,448,743 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Claims

1. An external memory coupled to a mass storage controller, the external memory comprising:

a plurality of first tables, each first table containing first metadata relating to a first area of flash memory controlled by the mass storage controller;

a plurality of second tables, each second table containing second metadata regarding a second area of flash memory controlled by the mass storage controller, each first area consisting of a subset of a second area, each second table further including a count for the number of portions of the second area which store invalid data and another count for the number of times a portion of the second area has been erased;

a third table, distinct from the first tables and second tables, the third table containing physical flash memory addresses associated with logical host addresses, the physical flash memory addresses identifying one of a plurality of flash ports that are part of the mass storage controller, wherein each flash port is connected to a group of flash memory devices; and

an interface to the mass storage controller, wherein the mass storage controller is configured to generate and store aggregated data in the external memory, the aggregated data including data stored in the plurality of first tables, the plurality of second tables, and the third table in the external memory.

2. The external memory of claim 1, wherein:

each first area consists of a segment of memory on a plurality of flash memory devices contained in one of the groups of flash memory devices.

3. The external memory of claim 2, wherein:

the first metadata includes metadata related to groups of flash memory pages within the first area.

4. The external memory of claim 3, wherein:

each group of flash memory pages consists of one page from each of a plurality of flash memory devices, each such page being located at the same address in each of the devices.

5. The external memory of claim 3, wherein:

the first metadata includes information relating to an absolute or relative time when data was written to a group of flash memory pages.

6. The external memory of claim 5, wherein:

the first metadata further includes information regarding whether specific flash memory pages or groups of flash memory pages have been identified as defective.

7. The external memory of claim 1, the external memory further including respective portions for storing:

first data received from a host for storage in flash memory; and

second data received from flash memory for transmission to the host.

8. The external memory of claim 1, wherein:

the plurality of second tables includes one table related to each flash port.

9. The external memory of claim 8, wherein:

for each second table, the second area is accessed by using the flash port to which the second table is related.

10. The external memory of claim 1, wherein:

the third table associates each physical flash memory address with a range of logical host addresses, wherein the logical host address range is related to the number of logical host addresses that correspond to data stored on a single flash memory page.

11. A method of operating a system, the system including a mass storage controller and an external memory coupled to the mass storage controller, the external memory comprising a plurality of first tables, a plurality of second tables, and a third table, the method comprising:

storing, in each respective first table of the plurality of first tables, first metadata relating to a first area of flash memory controlled by the mass storage controller;

storing, in each respective second table of the plurality of second tables,

second metadata regarding a second area of flash memory controlled by the mass storage controller, each first area consisting of a subset of a second area,

a count for the number of portions of the second area which store invalid data, and

another count for the number of times a portion of the second area has been erased;

storing, in the third table, distinct from the first tables and second tables, physical flash memory addresses associated with logical host addresses, the physical flash memory addresses identifying one of a plurality of flash ports that are part of the mass storage controller, wherein each flash port is connected to a group of flash memory devices; and

generating and storing aggregated data in the plurality of first tables, the plurality of second tables, and the third table in the external memory.

12. The method of claim 11, wherein:

each first area consists of a segment of memory on a plurality of flash memory devices contained in one of the groups of flash memory devices.

13. The method of claim 12, wherein:

the first metadata includes metadata related to groups of flash memory pages within the first area.

14. The method of claim 13, wherein:

each group of flash memory pages consists of one page from each of a plurality of flash memory devices, each such page being located at the same address in each of the devices.

15. The method of claim 13, wherein:

the first metadata includes information relating to an absolute or relative time when data was written to a group of flash memory pages.

16. The method of claim 15, wherein:

the first metadata further includes information regarding whether specific flash memory pages or groups of flash memory pages have been identified as defective.

17. The method of claim 11, wherein the external memory further includes respective portions for storing:

first data received from a host for storage in flash memory; and

second data received from flash memory for transmission to the host.

18. The method of claim 11, wherein:

the plurality of second tables includes one table related to each flash port.

19. The method of claim 18, wherein:

for each second table, the second area is accessed by using the flash port to which the second table is related.

20. The method of claim 11, wherein:

the third table associates each physical flash memory address with a range of logical host addresses, wherein the logical host address range is related to the number of logical host addresses that correspond to data stored on a single flash memory page.

21. A system including a mass storage controller and an external memory coupled to the mass storage controller, the system comprising:

one or more ports for coupling to one or more hosts;

the mass storage controller configured to be connected to flash memory and to generate and store aggregated data in the external memory; and

the external memory coupled to the mass storage controller, the external memory including;

an interface to the mass storage controller;

a plurality of first tables, each first table to store first metadata relating to a first area of the flash memory controlled by the mass storage controller;

a plurality of second tables, each second table to store second metadata regarding a second area of flash memory controlled by the mass storage controller, each first area consisting of a subset of a second area, each second table further including a count for the number of portions of the second area which store invalid data and another count for the number of times a portion of the second area has been erased; and

a third table, distinct from the first tables and second tables, the third table to store physical flash memory addresses associated with logical host addresses, the physical flash memory addresses identifying one of a plurality of flash ports that are part of the mass storage controller, wherein each flash port is configured to be connected to a group of flash memory devices.

22. The system of claim 21, wherein:

each first area consists of a segment of memory on a plurality of flash memory devices contained in one of the groups of flash memory devices.

23. The system of claim 22, wherein:

the first metadata includes metadata related to groups of flash memory pages within the first area.

24. The system of claim 23, wherein:

each group of flash memory pages consists of one page from each of a plurality of flash memory devices, each such page being located at the same address in each of the devices.

25. The system of claim 23, wherein:

the first metadata includes information relating to an absolute or relative time when data was written to a group of flash memory pages.

26. The system of claim 25, wherein:

the first metadata further includes information regarding whether specific flash memory pages or groups of flash memory pages have been identified as defective.

27. The system of claim 21, wherein the external memory further includes respective portions for storing:

first data received from a host for storage in flash memory; and

second data received from flash memory for transmission to the host.

28. The system of claim 21, wherein:

the plurality of second tables includes one table related to each flash port.

29. The system of claim 28, wherein:

for each second table, the second area is accessed by using the flash port to which the second table is related.

30. The system of claim 21, wherein:

the third table associates each physical flash memory address with a range of logical host addresses, wherein the logical host address range is related to the number of logical host addresses that correspond to data stored on a single flash memory page.