METHODS, DEVICES, AND SYSTEMS RELATED TO FORMING SEMICONDUCTOR POWER DEVICES WITH A HANDLE SUBSTRATE

• US 20140239348A1
• Filed: 02/22/2013
• Published: 08/28/2014
• Est. Priority Date: 02/22/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Schubert, Martin F., Odnoblyudov, Vladimir, Basceri, Cem
• Granted Patent: US 9,768,271 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

Claims

1. A method, comprising:

forming a semiconductor device assembly that includes;

a handle substrate;

a semiconductor structure having a first side and a second side opposite the first side; and

intermediary material between the semiconductor structure and the handle substrate;

removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure; and

removing at least a portion of the intermediary material via the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

2. The method of claim 1 wherein:

the opening in the semiconductor structure comprises a first trench;

the portion of the intermediary material comprises at least a first portion of the intermediary material adjacent the first trench;

removing material from the semiconductor structure further comprises forming a second trench that extends from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure, wherein the first and second trenches at least partially define a mesa in the semiconductor structure; and

removing the portion of the intermediary material further comprises removing via the first trench the first portion of the material and removing via the second trench at least a second portion of the intermediary material to decouple the semiconductor structure from the handle substrate.

3. The method of claim 2 wherein:

the handle substrate comprises a poly-Aluminum Nitride substrate (p-AlN); and

the method comprises forming a power transistor that includes the mesa formed in the semiconductor structure.

4. The method of claim 2, further comprising removing material from the semiconductor structure to mechanically isolate active regions in the semiconductor structure.

5. The method of claim 4 wherein:

the semiconductor structure comprises a first semiconductor material and a second semiconductor material; and

the second semiconductor material is between the first semiconductor material and the intermediary material; and

wherein the method further comprises removing material from the first semiconductor material of the semiconductor structure to form a third trench that exposes a surface of the second semiconductor material through the third trench.

6. The method of claim 1 wherein removing the intermediary material further comprises exposing the intermediary material to an etchant via the opening in the semiconductor structure.

7. The method of claim 6 wherein exposing the intermediary material to the etchant further comprises etching the intermediary material to form a gap between the semiconductor structure and the handle substrate.

8. The method of claim 6 wherein:

the method further comprises attaching a transfer structure to the semiconductor structure at the first side of the semiconductor structure; and

exposing the intermediary material to the etchant comprises decoupling the semiconductor structure from the handle substrate by etching the intermediary material with the transfer structure attached to the semiconductor structure.

9. The method of claim 1 wherein:

the first side of the semiconductor structure comprises an active region; and

the opening extends through an active region of the semiconductor structure.

10. A method of forming a semiconductor device assembly, comprising:

forming a stack of semiconductor materials on a handle substrate;

forming openings in the stack of semiconductor materials, wherein portions of the handle substrate are exposed through the openings; and

undercutting the stack of semiconductor materials adjacent the openings in the stack semiconductor materials.

11. The method of claim 10 wherein undercutting the portion of the stack of semiconductor materials comprises at least partially submerging the stack of semiconductor materials in an etchant.

12. The method of claim 10, further comprising forming a semiconductor device, wherein the semiconductor device includes at least a portion of the stack of semiconductor materials.

13. The method of claim 12 wherein the semiconductor device is a power transistor.

14. The method of claim 12 wherein the semiconductor device is a high electron mobility transistor (HEMT) device.

15. The method of claim 12 wherein the semiconductor device is a direct-attach device.

16. The method of claim 10 wherein undercutting the portion of the stack of semiconductor materials comprises decoupling the stack of semiconductor materials from the handle substrate.

17. The method of claim 16, further comprising

forming a semiconductor device to include at least a portion of the stack of semiconductor materials;

forming a first electrical contact at a first side of the semiconductor device; and

forming a second electrical contact at a second side of the semiconductor device that is opposite the first side of the semiconductor device.

18. The method of claim 10, further comprising forming a semiconductor device to include at least a portion of the stack of semiconductor materials and a portion of the handle substrate.

19. A semiconductor device assembly, comprising:

a handle substrate;

semiconductor structure having a first side and a second side opposite the first side; and

intermediary material between the handle substrate and the second side of the semiconductor structure,

wherein;

the semiconductor structure includes an opening that extends from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure; and

the handle substrate and a portion of the semiconductor structure at the second side of the semiconductor structure are separated by a gap in the intermediary material adjacent to the opening.

20. The semiconductor device assembly of claim 19 wherein:

the first side of the semiconductor structure comprises an active region; and

the opening is positioned within the active region.

21. The semiconductor device assembly of claim 20 wherein the active region includes a gate region of the semiconductor structure.

22. The semiconductor device assembly of claim 20 wherein the active region includes a source or drain region of the semiconductor structure.

23. The semiconductor device assembly of claim 19 wherein the semiconductor structure comprises at least a portion of power transistor device.

24. The semiconductor device assembly of claim 19 wherein the semiconductor structure comprises at least a portion high electron mobility transistor (HEMT) device.

25. The semiconductor device assembly of claim 19 wherein the handle substrate comprises a poly-Aluminum Nitride (p-AlN) substrate.

26. A semiconductor transistor device, comprising a stack of semiconductor materials that includes:

a semiconductor material;

a source region, a gate region, and a drain region formed in the semiconductor material; and

a trench between the source and drain regions.

27. The semiconductor transistor device of claim 26 wherein the trench extends through the gate region.

28. The semiconductor transistor device of claim 26 wherein the stack of semiconductor materials includes a first side and a second side opposite the first side, and wherein the semiconductor transistor device further comprises a first electrical contact at the first side that is electrically coupled to the gate region and a second electrical contact at the second side that is electrically coupled to at least one of the source region or the drain region.

29. The semiconductor device of claim 26 wherein the trench includes a first sidewall adjacent the source region and a second sidewall adjacent the drain region.