GRAPHICS PROCESSING UNIT WITH A TEXTURE RETURN BUFFER AND A TEXTURE QUEUE

• US 20140240337A1
• Filed: 02/26/2013
• Published: 08/28/2014
• Est. Priority Date: 02/26/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Lindholm, John Erik
• Granted Patent: US 9,171,525 B2
• Time in Patent Office: Days
• US Class Current: 345/582
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A processor and a system are provided for performing texturing operations loaded from a texture queue that provides temporary storage of texture coordinates and texture values. The processor includes a texture queue implemented in a memory of the processor, a crossbar coupled to the texture queue, and one or more texture units coupled to the texture queue via the crossbar. The crossbar is configured to reorder texture coordinates for consumption by the one or more texture units and to reorder texture values received from the one or more texture units.

Claims

1. A processor comprising:

a texture queue implemented in a memory of the processor,

a crossbar coupled to the texture queue; and

one or more texture units coupled to the texture queue via the crossbar,

wherein the crossbar is configured to reorder texture coordinates for consumption by the one or more texture units and to reorder texture values received from the one or more texture units.

2. The processor of claim 1, wherein the processor further comprises a scheduler unit.

3. The processor of claim 2, wherein the scheduler unit is configured to dynamically allocate memory spaces in the texture queue, each memory space associated with a particular batch of texture operations for one or more quads of a particular pixel tile.

4. The processor of claim 1, wherein the texture queue is configured to store one or more texture coordinates for transmission to at least one of the one or more texture units.

5. The processor of claim 1, wherein each texture unit in the one or more texture units is configured to drain a number of texture coordinates from the texture queue in parallel.

6. The processor of claim 1, wherein the texture queue comprises a first portion of memory for storing texture coordinates for transmission to the one or more texture units and a second portion of memory for storing texture values received from the one or more texture units.

7. The processor of claim 6, wherein the texture coordinates are drained from the texture queue according to a TexTile priority mode.

8. The processor of claim 6, wherein the texture coordinates are drained from the texture queue according to a QuadTex priority mode.

9. The processor of claim 6, wherein the texture queue is coupled to a first texture interface buffer configured to reorder texture coordinates for consumption by the one or more texture units.

10. The processor of claim 9, wherein the texture queue is coupled to a second texture interface buffer configured to reorder texture values received from the one or more texture units for transmission to the texture queue.

11. The processor of claim 1, wherein the one or more texture units are configured to generate texture values that represent filtered values generated by sampling a texture map.

12. The processor of claim 1, wherein each of the one or more texture units comprises:

a texture filtering unit configured to filter sampled texture data to generate a texture value that is transmitted to the texture queue;

a texture address unit configured to generate one or more physical addresses based on one or more texture coordinates associated with a texture operation; and

a texture latency FIFO (First-in, First-out) coupled to the texture address unit and configured to buffer texture operations while sampled texture data is fetched from memory locations corresponding to the one or more physical addresses.

13. The processor of claim 1, wherein the processor is a graphics processing unit.

14. A system comprising:

a processor comprising;

a texture queue implemented in a memory of the processor,

a crossbar coupled to the texture queue; and

one or more texture units coupled to the texture queue via the crossbar,

wherein the crossbar is configured to reorder texture coordinates for consumption by the one or more texture units and to reorder texture values received from the one or more texture units.

15. The system of claim 14, wherein the processor further comprises a scheduler unit configured to dynamically allocate memory spaces in the texture queue, each memory space associated with a particular batch of texture operations for one or more quads of a particular pixel tile.

16. The system of claim 14, wherein the texture queue comprises a first portion of memory for storing texture coordinates for transmission to the one or more texture units and a second portion of memory for storing texture values received from the one or more texture units.

17. The system of claim 14, wherein each of the one or more texture units comprises:

a texture filtering unit configured to filter sampled texture data to generate a texture value that is stored in a slot of the texture return buffer;

a texture address unit configured to generate one or more physical addresses based on one or more texture coordinates associated with a texture operation; and

a texture latency FIFO (First-in, First-out) coupled to the texture address unit and configured to buffer texture operations while sampled texture data is fetched from memory locations corresponding to the one or more physical addresses.

18. The system of claim 14, wherein the texture queue is coupled to a first texture interface buffer configured to reorder texture coordinates for consumption by the one or more texture units.

19. The system of claim 14, wherein the processor comprises a graphics processing unit.

20. The system of claim 14, wherein the processor is included in a system-on-chip (SoC).