INTERCONNECTIONS FOR 3D MEMORY
First Claim
Patent Images
1. An apparatus, comprising:
- a stack of materials including a plurality of pairs of materials, pairs of materials including a conductive line formed over an insulation material, the stack of materials having a stair step structure formed at one edge extending in a first direction, a stair step including one of the pairs of materials;
a first interconnection coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step; and
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Abstract
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.
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Citations
36 Claims
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1. An apparatus, comprising:
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a stack of materials including a plurality of pairs of materials, pairs of materials including a conductive line formed over an insulation material, the stack of materials having a stair step structure formed at one edge extending in a first direction, a stair step including one of the pairs of materials; a first interconnection coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step; and - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of forming a memory, comprising:
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forming a stack of pairs of materials, the pairs of materials including a conductive line formed over an insulation material, the conductive line having a longest dimension in a first direction, the stack of pairs of materials having a wide width portion and a narrow width portion; forming a stair step structure on one edge of the stack of pairs of materials; forming an ascending interconnection coupled to the conductive line at a stair step; and forming a top planar interconnection coupled to an ascending interconnection, wherein the top planar interconnection has a longest dimension in a direction different than the first direction. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. An apparatus, comprising:
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a memory array having a stack of conductive lines with a wide width portion and a narrow width portion, the narrow width portion having a stair step structure; and a controller coupled to the memory array, the controller configured to control; performing a number of operations; and equalizing potential of access lines for a block of the memory array after the of number of operations is completed, wherein the stack of conductive lines is coupled to circuitry below the memory array through top planar interconnections coupled between ascending interconnections and descending interconnections, the top planar interconnections have a longest dimension in a direction different from a direction of a longest dimension of the conductive lines. - View Dependent Claims (22, 23, 24, 25)
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26. An apparatus, comprising:
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a vertical string of memory cells coupled to a data line; a plurality of access lines coupled to the memory cells and control circuitry; and a switchable conductive path arranged between the plurality of access lines, wherein the plurality of access lines are coupled to the control circuitry through interconnections formed of a same material as the plurality of access lines, the interconnections located in a plane parallel to planes in which the plurality of access lines are formed and having a longest dimension in a direction different from a direction of a longest dimension of the plurality of access lines. - View Dependent Claims (27, 28)
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29. A method of operating a memory, comprising:
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performing a read operation or a program operation; equalizing potential of access lines for a block of the memory after the read operation or the program operation is completed; and setting potential of equalized access lines for the block of the memory to a reference potential, wherein the memory is a three dimensional memory including a stack of access lines configured to have a stair step structure on an edge, the access lines being coupled to circuitry controlling the equalizing through an interconnection formed of a same material as the access lines and having a longest dimension in a direction substantially perpendicular to a direction of a longest dimension of the access lines. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
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Specification