INTERCONNECTIONS FOR 3D MEMORY

• US 20140241026A1
• Filed: 02/22/2013
• Published: 08/28/2014
• Est. Priority Date: 02/22/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Granted Patent: US 9,111,591 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

Claims

1. An apparatus, comprising:

a stack of materials including a plurality of pairs of materials, pairs of materials including a conductive line formed over an insulation material, the stack of materials having a stair step structure formed at one edge extending in a first direction, a stair step including one of the pairs of materials;

a first interconnection coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step; and

2. The apparatus of claim 1, further comprising a second interconnection coupled to the first interconnection, the second interconnection extending in a third direction substantially perpendicular to both the first and second directions.

3. The apparatus of claim 2, wherein the second interconnection does not extend beyond a rectangular area bounded on one side by the stack of materials and bounded on a second side by the stair step structure.

4. The apparatus of claim 2, further comprising a third interconnection coupled to the second interconnection, the third interconnection extending in a direction opposite the second direction, the third interconnection being substantially parallel with the first interconnection.

5. The apparatus of claim 4, wherein the third interconnection extends to an elevation below the stack of materials.

6. The apparatus of claim 4, further comprising a fourth interconnection coupled to the third interconnection, the fourth interconnection extending in the first direction.

7. The apparatus of claim 4, further comprising a fourth interconnection coupled to the third interconnection, the fourth interconnection extending in a direction opposite the first direction.

8. The apparatus of claim 4, wherein the fourth interconnection extends underneath the stack of materials.

9. The apparatus of claim 2, wherein the second interconnection is arranged such that a pitch of the second interconnection is independent of a width of the stack of materials in the second direction.

10. The apparatus of claim 1, wherein the stack of materials has a first width in a direction perpendicular to the first direction, and the stair step structure has a second width in a direction perpendicular to the first direction, the second width being less than the first width.

11. The apparatus of claim 10, wherein a stair step of the stair step structure extends in the first direction a length corresponding to the pitch of the second interconnection.

12. A method of forming a memory, comprising:

forming a stack of pairs of materials, the pairs of materials including a conductive line formed over an insulation material, the conductive line having a longest dimension in a first direction, the stack of pairs of materials having a wide width portion and a narrow width portion;

forming a stair step structure on one edge of the stack of pairs of materials;

forming an ascending interconnection coupled to the conductive line at a stair step; and

forming a top planar interconnection coupled to an ascending interconnection,

wherein the top planar interconnection has a longest dimension in a direction different than the first direction.

13. The method of claim 12, further comprising forming a descending interconnection coupled to the top planar interconnection.

14. The method of claim 13, further comprising forming a bottom planar interconnection coupled to the descending interconnection, wherein the bottom planar interconnection has a longest dimension in the first direction.

15. The method of claim 14, wherein a first bottom planar interconnection extends in a first radial direction from a descending interconnection, and a second bottom planar interconnection extends in a second radial direction from a descending interconnection, the second radial direction being different from the first radial direction.

16. The method of claim 14, wherein the second radial direction is an opposite radial direction from the first radial direction.

17. The method of claim 14, wherein the bottom planar interconnection has a longest dimension in the first direction.

18. The method of claim 13, wherein forming the stack of pairs of materials includes removing a portion of the stack of pairs of materials in an area adjacent to the wide width portion and the narrow width portion.

19. The method of claim 18, wherein removing the portion of the stack of pairs of materials occurs after forming the stair step structure, the area including a portion of the stair step structure.

20. The method of claim 18, wherein the descending interconnections pass within the area.

21. An apparatus, comprising:

a memory array having a stack of conductive lines with a wide width portion and a narrow width portion, the narrow width portion having a stair step structure; and

a controller coupled to the memory array, the controller configured to control;

performing a number of operations; and

equalizing potential of access lines for a block of the memory array after the of number of operations is completed,

wherein the stack of conductive lines is coupled to circuitry below the memory array through top planar interconnections coupled between ascending interconnections and descending interconnections, the top planar interconnections have a longest dimension in a direction different from a direction of a longest dimension of the conductive lines.

22. The apparatus of claim 21, wherein the conductive lines, the ascending interconnections, the descending interconnections, and the top planar interconnections are all formed of a same conductive material.

23. The apparatus of claim 21, wherein the stack of conductive lines are coupled to circuitry below the memory array through bottom planar interconnections located below the memory array coupled to the descending interconnections.

24. The apparatus of claim 21, wherein the descending interconnections have a longest dimension in a direction substantially the same as the direction of the longest dimension of the conductive lines.

25. The apparatus of claim 21, wherein the controller is configured to control setting potential of equalized access lines of the block of memory array to a reference potential.

26. An apparatus, comprising:

a vertical string of memory cells coupled to a data line;

a plurality of access lines coupled to the memory cells and control circuitry; and

a switchable conductive path arranged between the plurality of access lines,

wherein the plurality of access lines are coupled to the control circuitry through interconnections formed of a same material as the plurality of access lines, the interconnections located in a plane parallel to planes in which the plurality of access lines are formed and having a longest dimension in a direction different from a direction of a longest dimension of the plurality of access lines.

27. The apparatus of claim 26, wherein the switchable conductive path includes a number of switches arranged between pairs of access lines such that the plurality of access lines are selectably coupled together through the number of switches.

28. The apparatus of claim 27, further comprising:

a select gate device in series with the data line at an end of the vertical string of memory cells; and

a select gate line coupled to the select gate device,

wherein a particular one of the number of switches is arranged between a particular one of the plurality of access lines and the select gate line such that the select gate line can be shorted together with the plurality of access lines.

29. A method of operating a memory, comprising:

performing a read operation or a program operation;

equalizing potential of access lines for a block of the memory after the read operation or the program operation is completed; and

setting potential of equalized access lines for the block of the memory to a reference potential,

wherein the memory is a three dimensional memory including a stack of access lines configured to have a stair step structure on an edge, the access lines being coupled to circuitry controlling the equalizing through an interconnection formed of a same material as the access lines and having a longest dimension in a direction substantially perpendicular to a direction of a longest dimension of the access lines.

30. The method of claim 29, further comprising discharging the access lines to a ground reference potential after equalizing.

31. The method of claim 30, further comprising biasing the access lines to potentials different than the reference potential after discharging.

32. The method of claim 31, wherein biasing the access lines to potentials different than the reference potential includes biasing the access lines each to a different potential.

33. The method of claim 29, wherein equalizing the access lines includes coupling all of the access lines together.

34. The method of claim 29, further comprising biasing the access lines each to a different potential after equalizing.

35. The method of claim 29, further comprising equalizing a plurality of select gate lines of the memory array to the same potential.

36. The method of claim 35, wherein equalizing the plurality of select gate lines includes coupling the plurality of select gate lines to the access lines.