TRACKING CIRCUIT

• US 20140241077A1
• Filed: 02/28/2013
• Published: 08/28/2014
• Est. Priority Date: 02/28/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: KATOCH, Atul, TAYAL, Mayank
• Granted Patent: US 8,929,160 B2
• Time in Patent Office: Days
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined.

Claims

1. A method comprising:

determining a current flowing through a voltage line and/or a data line in a column of a tracking circuit;

determining a threshold tracking time delay of the tracking circuit; and

based on the determined current flowing through the voltage line and/or the data line and the threshold tracking time delay, determining a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns.

2. The method of claim 1, wherein

determining the threshold tracking time delay is based on a statistical distribution of a plurality of time delays of a plurality of memory cells.

3. The method of claim 1, wherein

determining the threshold tracking time delay is based on a worst case time delay of a plurality of time delays of a plurality of memory cells.

4. The method of claim 1, wherein

a first cell of the number of first cells includes a first transistor coupled in series with a second transistor;

the first transistor and the second transistor cause a delay time on a tracking data line associated with the first cell of the number of first cells;

a memory cell to be tracked by the tracking circuit includes a third transistor and a fourth transistor; and

the third transistor and the fourth transistor cause a time delay on a memory data line associated with the memory cell to be tracked.

5. The method of claim 1, wherein

determining the number of columns in the tracking circuit, the number of first cells in each column of the plurality of columns, and each number of second cells in the each column of the plurality of columns comprises

adding a first tracking cell to a first column until a first number of first tracking cells in the first column reaches a number specified for the first column;

calculating the number of second cells in the first column;

adding another tracking cell to a second column; and

calculating the number of second cells in the second column.

6. A method comprising:

determining a threshold tracking time delay of a tracking circuit having a plurality of columns;

determining a current flowing through a first tracking cell of the tracking circuit, wherein the current corresponds to a tracking time delay of the first tracking cell; and

based on the determined threshold tracking time delay and the determined current flowing through the first tracking cell, performing the following operations

providing a plurality of first tracking cells to a first column of the tracking circuit, wherein a number of the plurality of first tracking cells is based on a current drawn by the plurality of first tracking cells and a current handling capacity of a data line and/or a voltage line of the first column; and

providing at least one other first tracking cell to a second column of the tracking circuit.

7. The method of claim 6, wherein

the current flowing through the first tracking cell flows through the data line, a first transistor of the first tracking cell, a second transistor of the tracking cell, and the voltage line.

8. The method of claim 6, further comprising

providing at least one second tracking cells to the first column of the tracking circuit,

wherein

a number of the plurality of first tracking cells plus a number of the at least one second tracking cells equal a number of rows in a memory array of a memory macro.

9. The method of claim 6, further comprising

providing at least one second tracking cells to the second column of the tracking circuit,

wherein

a number of the at least one first tracking cell plus a number of the at least one second tracking cells equal a number of rows in a memory array of a memory macro.

10. The method of claim 6, wherein

a first cell of the number of first cells includes a first transistor coupled in series with a second transistor;

the first transistor and the second transistor cause a delay time on a tracking data line associated with the first cell of the number of first cells;

a memory cell to be tracked by the tracking circuit includes a third transistor and a fourth transistor; and

the third transistor and the fourth transistor cause a time delay on a memory data line associated with the memory cell to be tracked.

11. A method comprising:

determining a threshold tracking time delay of a tracking circuit having a plurality of columns;

determining a current flowing through a first tracking cell of the tracking circuit, wherein the current corresponds to a tracking time delay of the first tracking cell;

based on the threshold tracking time delay and the tracking time delay of the first tracking cell, determining a number of first tracking cells for use in the tracking circuit; and

distributing the determined number of first tracking cells in a plurality of columns, wherein a current drawn by a number of first tracking cells in a column of the plurality of columns is subject to a current value predetermined on a tracking data line and/or a tracking voltage line, and the current drawn by the number of first tracking cells in the column flowing through the tracking data line or the tracking voltage line.

12. The method of claim 11 wherein

determining the threshold tracking time delay is based on a statistical distribution of a plurality of time delays of a corresponding plurality of memory cells.

13. The method of claim 11, wherein

the first tracking cell includes a first transistor coupled in series with a second transistor;

the first transistor is coupled with the tracking data line;

the second transistor is coupled with the voltage line; and

the current flowing through the first tracking cell flows through the tracking data line, the first transistor, the second transistor, and the tracking voltage line.

14. The method of claim 11, wherein

the first tracking cell includes a first transistor coupled in series with a second transistor;

the first transistor and the second transistor cause a time delay on a tracking data line associated with the first cell of the number of first cells;

a second tracking cell includes a third transistor coupled in series with a fourth transistor; and

the third transistor is turned off when the tracking circuit is in operation.

15. The method of claim 11, wherein

the tracking circuit further comprises a plurality of second cells;

and

the method further comprises distributing the plurality of second cells in the plurality of columns.

16. The method of claim 11, wherein

distributing the determined number of first tracking cells in a plurality of columns comprises

adding a first tracking cell to a first column until a first number of first tracking cells in the first column reaches a number specified for the first column;

and

adding another tracking cell to a second column.

17. The method of claim 11, wherein

a first cell of the number of first cells includes a first transistor coupled in series with a second transistor;

the first transistor and the second transistor cause a delay time on a tracking data line associated with the first cell of the number of first cells;

a memory cell to be tracked by the tracking circuit includes a third transistor and a fourth transistor; and

the third transistor and the fourth transistor cause a delay time on a memory data line associated with the memory cell to be tracked.

18. A method comprising:

determining a threshold tracking time delay of a tracking circuit; and

based on a number of first tracking cells in the tracking circuit, causing a tracking time delay substantially equal to the threshold tracking time delay,

wherein

the tracking circuit includes a plurality of columns;

a first column of the plurality of columns includes

at least one first tracking cell; and

at least one second tracking cell;

a second column of the plurality of columns includes

at least another first tracking cell; and

at least another second tracking cell;

a number of the at least one first tracking cell of the first column is based on a current drawn by the at least one first tracking cell in the first column and a current-handling capability of a tracking data line and/or a voltage line associated with the first column; and

the number of the at least one first tracking cell of the first column and a number of the at least one second tracking cell of the first column equal a number of rows of a memory array of a memory macro.

19. The method of claim 18, wherein

causing a tracking time delay substantially equal to the threshold tracking time delay comprises activating a tracking data line of the tracking circuit;

and

the tracking data line is coupled with each gate of each transistor of the at least one first tracking cell and of the at least another tracking cell.

20. The method of claim 18, wherein

a first tracking cell includes a first transistor coupled in series with a second transistor;

the first transistor and the second transistor cause a time delay on a tracking data line associated with the first cell of the number of first cells;

a second tracking cell includes a third transistor coupled in series with a fourth transistor; and

the third transistor is turned off when the tracking circuit is in operation.