SEMICONDUCTOR MEMORY DEVICE CAPABLE OF TESTING SIGNAL INTEGRITY

• US 20140244864A1
• Filed: 08/02/2013
• Published: 08/28/2014
• Est. Priority Date: 02/26/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SHIGA, Hitoshi
• Granted Patent: US 8,843,674 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry

Abstract

According to one embodiment, a semiconductor memory device includes a memory cell array, a first buffer, a second buffer, an interface unit and a controller. Data is transferred between the interface unit and the first buffer. The controller controls the first buffer, the second buffer and the interface unit. When receiving a first command and first data at a test time, the controller transfers the first data to the first buffer via the interface unit. When receiving a second command as a dummy command, the controller reads second data from the memory cell array to the second buffer and, at the same time, outputs first data held in the first buffer via the interface unit.

Claims

1. A semiconductor memory device comprising:

a memory cell array;

a first buffer;

a second buffer;

an interface unit, data being transferred between the interface unit and the first buffer; and

a controller configured to control the first buffer, the second buffer and the interface unit;

wherein the controller transfers first data to the first buffer via the interface unit when receiving the first data and a first command at a test time, reads second data from the memory cell array to the second buffer when receiving a second command as a dummy command and, at a same time, outputs the first data held in the first buffer via the interface unit;

wherein the first data is transferred to the first buffer according to a first clock signal with a first frequency, and the first data is output from the first buffer via the interface unit according to a second clock signal with a second frequency higher than the first frequency at the test time.

2-3. -3. (canceled)

4. A semiconductor memory device comprising:

a memory cell array;

a first buffer;

a second buffer;

an interface unit, data being transferred between the interface unit and the first buffer; and

a controller configured to control the first buffer, the second buffer and the interface unit;

wherein the controller generates expected value data according to a first command and causes the second buffer to hold the expected value data at a test time; and

wherein the controller transfers test data supplied via the interface unit to the first buffer according to a second command, compares the expected value data held in the second buffer with test data held in the first buffer according to a third command to hold a result of the comparison as status data, and outputs the status data according to a fourth command.

7. The device according to claim 4, wherein the test data is transferred to the first buffer according to a first clock signal with a first frequency.

5-6. -6. (canceled)

8. (canceled)

9. A semiconductor memory device comprising:

a memory cell array;

a first buffer;

a second buffer;

an interface unit, data being transferred between the interface unit and the first buffer; and

a controller configured to control the first buffer, the second buffer and the interface unit;

wherein the controller generates test data according to a first command, causes the first buffer to hold the test data at a test time, and outputs the test data held in the first buffer via the interface unit according to a second command.

10. The device according to claim 9, wherein the test data is output from the first buffer according to a first clock signal with a first frequency.

11. A semiconductor memory device comprising:

a memory cell array;

a first buffer;

a second buffer;

an interface unit;

a data controller connected to the interface unit;

a first data bus and a second data bus connected to the data controller, the first data bus being connected to even-numbered columns of the first buffer and the second data bus being connected to odd-numbered columns of the first buffer; and

a controller configured to control the first buffer, the second buffer, the interface unit and the data controller;

wherein the data controller alternately selects the first and second buffers at a data input time and output time.

12. The device according to claim 11, wherein the controller generates expected value data according to a first command, causes the second buffer to hold the expected value data at a test time, transfers test data supplied via the interface unit to the first buffer according to a second command, compares the expected value data held in the second buffer with test data held in the first buffer according to a third command to hold a result of the comparison as status data, and outputs the status data according to a fourth command.

13. The device according to claim 12, wherein the test data is transferred to the first buffer according to a first clock signal with a first frequency.

14. The device according to claim 11, wherein the controller generates test data according to a first command, causes the first buffer to hold the test data, and outputs test data held in the first buffer via the interface unit according to a second command.

15. The device according to claim 14, wherein the test data is output from the first buffer according to a first clock signal with a first frequency.