MEMORY DEVICE AND COMPUTER SYSTEM
First Claim
Patent Images
1. A memory device comprising:
- a non-volatile storage device from which data is read and to which data is written in response to a request from a host device;
an interface that is connected to the host device by a multiple upstream lanes and/or a multiple downstream lanes and performs data communication in both directions with the host device; and
a memory controller that controls the non-volatile storage device and the interface,wherein the memory controller includes a lane change unit that changes a connection state of each lane on the basis of lane settings which are used for communication with the host device and are determined on the basis of at least one of an amount of data transmitted and the sequentiality of data when the data is transmitted between the memory device and the host device.
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Abstract
A memory device according to an embodiment includes a non-volatile storage device from which data is read and to which data is written, an interface that is connected to the host device by a multiple upstream lanes and/or a multiple downstream lanes and performs data communication in both directions with the host device, and a memory controller. The memory controller changes a connection state of each lane on the basis of lane settings which are determined on the basis of at least one of an amount of data transmitted and the sequentiality of data when the data is transmitted between the memory device and the host device.
19 Citations
20 Claims
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1. A memory device comprising:
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a non-volatile storage device from which data is read and to which data is written in response to a request from a host device; an interface that is connected to the host device by a multiple upstream lanes and/or a multiple downstream lanes and performs data communication in both directions with the host device; and a memory controller that controls the non-volatile storage device and the interface, wherein the memory controller includes a lane change unit that changes a connection state of each lane on the basis of lane settings which are used for communication with the host device and are determined on the basis of at least one of an amount of data transmitted and the sequentiality of data when the data is transmitted between the memory device and the host device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer system comprising:
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a host device; and a memory device that performs data communication in both directions with the host device, wherein the memory device includes; a non-volatile storage device from which data is read and to which data is written in response to a request from a host device; a first interface that is connected to the host device by a multiple upstream lanes and/or a multiple downstream lanes and performs the data communication with the host device; and a memory controller that controls the non-volatile storage device and the first interface, the memory controller includes a first lane change unit that changes a connection state of each lane in the first interface, on the basis of lane settings which are used for communication with the host device and are determined on the basis of at least one of an amount of data transmitted and the sequentiality of data during the data transmission with the host device, and the host device includes; a second interface that is connected to the memory device by the multiple lanes and performs data communication with the memory device; and a second lane change unit that changes the connection state of each lane in the second interface on the basis of the lane settings. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification