Way Lookahead

• US 20140244933A1
• Filed: 02/28/2013
• Published: 08/28/2014
• Est. Priority Date: 02/28/2013
• Status: Active Grant

• Current Assignee: MIPS Tech, LLC
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Sudhakar, Ranganathan, Pota, Parthiv
• Granted Patent: US 9,720,840 B2
• Time in Patent Office: Days
• US Class Current: 711/125
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set associative cache is configured to store instructions. The instruction fetch unit is in communication with the n-way set associative cache and is configured to power up a first way, where a first indication is associated with an instruction and indicates the way where a future instruction is located and where the future instruction is two or more instructions ahead of the current instruction.

Claims

1. An apparatus comprising:

a n-way set associative cache configured to store instructions; and

an instruction fetch unit, in communication with the n-way set associative cache, configured to use a first indicator to power up a first way;

wherein;

the first indication is associated with an instruction and indicates where a future instruction is located; and

wherein the future instruction is two or more instructions ahead of the instruction.

2. An apparatus of claim 1, wherein the instruction fetch unit is pipelined.

3. An apparatus of claim 2, wherein:

the instruction fetch unit is divided into four pipelined stages;

a second stage retrieves the first indicator; and

a third stage identifies the way of the future instruction using the indicator.

4. An apparatus of claim 1, wherein the first indicator is stored as a prefix to a first instruction.

5. An apparatus of claim 1, wherein the first indicator is stored in a way lookahead buffer.

6. An apparatus of claim 1, further comprising a branch taken buffer (BTB) wherein the BTB comprises a second indicator indicting a second way where an instruction after a branch is located if the branch is taken and wherein the instruction fetch unit is further configured to use the BTB to power up the second way.

7. An apparatus of claim 6, wherein the instruction fetch unit chooses between using the first indicator or the second indicator to determine which way to power up based on a BTB prediction.

8. An apparatus of claim 6, wherein the BTB further comprises a third indicator of where a third way for a next-to-target instruction is located and wherein the instruction fetch unit is configured to use the third indicator to power up the third way.

9. An apparatus of claim 8, wherein the instruction fetch unit chooses between using the first indicator or the third indicator to determine which way to power up based on a BTB prediction.

10. An apparatus of claim 8, wherein the third indicator further comprises ways for instructions after the next-to-target instruction.

11. An apparatus of claim 1, wherein the n-way set associative cache is a 2-, 4-, or 8-way set associative cache.

12. An apparatus of claim 1, wherein the instruction are stored in the n ways of the n-way set associate cache based on the lower byte of the instruction pointer.

13. The method comprising:

calculating an instruction pointer for a first instruction;

reading a first tag associated with the instruction pointer;

determining a way for a future instruction two or more instructions ahead of the first instruction using the first tag; and

powering up the way at an appropriate time for a processor to read the future instruction.

14. The method of claim 13 further comprising powering down ways not determined at the appropriate time.

15. The method of claim 13, wherein the determining happens prior to the reading the future instruction.

16. The method of claim 13, further comprising a second tag that is part of a branch target buffer (BTB) entry for the first instruction.

17. The method of claim 16, wherein the determining chooses between the first and second tag based on a branch prediction from the BTB.

18. The method of claim 16, wherein the predicted way comprises another predicted way for the next-to-target instruction.

19. A non-transitory computer readable storage medium having encoded thereon computer readable program code for generating a computer processor comprising:

a n-way set associative cache configured to store instructions; and

an instruction fetch unit, in communication with the n-way set associative cache, configured to use a first indicator to power up a first way;

wherein;

the first indication is associated with an instruction and indicates where a future instruction is located; and

wherein the future instruction is two or more instructions ahead of the instruction.

20. The non-transitory computer readable storage medium having encoded thereon computer readable program code for generating a computer processor of claim 19, further comprising a branch taken buffer (BTB) wherein the BTB comprises a second indicator indicting a second way where an instruction after a branch is located if the branch is taken and wherein the instruction fetch unit is further configured to use the BTB to power up the second way.