SEMICONDUCTOR MEMORY DEVICES INCLUDING ERROR CORRECTION CIRCUITS AND METHODS OF OPERATING THE SEMICONDUCTOR MEMORY DEVICES

• US 20140245105A1
• Filed: 06/05/2013
• Published: 08/28/2014
• Est. Priority Date: 02/26/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hak-Soo Yu, Hoi Ju Chung, Jae-Youn Youn, Su-A Kim
• Inventors: KIM, Su-A, YU, Hak-Soo, YOUN, Jae-Youn, CHOI, Hyo-Jin, CHUNG, Hoi-ju, SEO, Mu-Jin
• Granted Patent: US 9,268,636 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/783 with refresh of replacement cells, e.g. in DRAMs

Abstract

A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

Claims

1. A memory controller comprising:

a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data.

2. The memory controller of claim 1, wherein the controller input/output circuit is configured to output the second command in response to received correction status information.

3. The memory controller of claim 2, wherein the correction status information indicates whether a number of error bits in the first data is greater than or equal to a threshold value.

4. The memory controller of claim 1, wherein the controller input/output circuit is further configured to output at least one additional command between the output of the first and second commands.

5. The memory controller of claim 1, wherein the controller input/output circuit is further configured to output address information associated with the first data.

6. The memory controller of claim 5, wherein the controller input/output circuit is further configured to output at least one additional command and associated address information between the output of the first and second commands.

7. The memory controller of claim 1, wherein the second command is a buffer read command.

8-15. -15. (canceled)

16. A memory device comprising:

an error correction circuit configured to correct errors in data read from a memory cell in response to a first command; and

a data output circuit configured to output the corrected data in response to a second command.

17. The memory device of claim 16, further comprising:

an error detector configured to detect a number of error bits in the read data in response to the first command;

wherein

the error correction circuit is configured to correct the errors in the read data based on the detected number of error bits.

18. The memory device of claim 17, wherein the error correction circuit is further configured to use one of a first error correction algorithm and a second error correction algorithm based on the detected number of error bits.

19. The memory device of claim 17, wherein the error detector is configured to compare the detected number of error bits with at least one threshold value, and wherein the error correction circuit is configured to correct the errors in the read data based on the comparison.

20. The memory device of claim 19, wherein the error correction circuit is configured to correct the errors in the data using a first error correction algorithm if the detected number of error bits is greater than or equal to a first threshold value, and wherein the error correction circuit is configured to correct the errors in the data using a second error correction algorithm if the detected number of error bits is greater than a second threshold value, but less than the first threshold value.

21. The memory device of claim 16, further comprising:

an error correction status information generating circuit configured to output error correction status information based on the detected number of error bits.

22. The memory device of claim 21, wherein the error correction status information indicates whether the detected number of error bits is greater than or equal to a first threshold value.

23. The memory device of claim 21, wherein the error correction status information indicates whether the read data is correctable.

24. The memory device of claim 16, wherein the second command is one of a read command and a buffer read command.

25. The memory device of claim 16, further comprising:

a memory cell array including the memory cell.

26. The memory device of claim 16, further comprising:

a data storage circuit configured to store the read data to be corrected by the error correction circuit;

wherein

the data output circuit is configured to output the corrected data from the data storage circuit in response to the second command.

27. The memory device of claim 26, wherein the data storage circuit is further configured to store a buffer status indicator in association with the read data.

28. The memory device of claim 26, further comprising:

a management circuit configured to control output of the read data from the data storage circuit to the data output circuit based on the second command.

29. The memory device of claim 28, wherein the data storage circuit includes a plurality of data buffers, and wherein the management circuit is configured to control output of the stored data from the plurality of data buffers to the data output circuit based on the second command and address information associated with the second command.

30. The memory device of claim 26, further comprising:

an address matching circuit configured to output a matching signal based on a comparison between address information associated with the second command and address information associated with the data stored in the data storage circuit; and

a management circuit configured to control output of the read data from the data storage circuit to the data output circuit based on the matching signal.

31. The memory device of claim 30, wherein the data storage circuit includes a plurality of data buffers, and wherein the address matching circuit is configured to output the matching signal based on a comparison between address information associated with the second command and address information stored in association with the data stored in the plurality of data buffers.

32. The memory device of claim 31, wherein the management circuit controls the data storage circuit to output the stored data to the data output circuit if the address information associated with the second command matches address information associated with the stored data.

33-89. -89. (canceled)

90. A method of operating a memory device, the method comprising:

correcting errors in data read from a memory cell in response to a first command; and

outputting the corrected data in response to a second command.

91. The method of claim 90, further comprising:

detecting a number of error bits in data read from the memory cell in response to the first command; and

storing the read data if the detected number of error bits is greater than or equal to a first threshold value.

92. The method of claim 90, further comprising:

detecting a number of error bits in data read from the memory cell in response to the first command; and

outputting error correction status information associated with the read data, the error correction status information indicating whether the detected number of error bits is greater than or equal to a first threshold value.

93. The method of claim 91, further comprising:

checking a data storage status indicator in response to the second command, the data storage status indicator indicating whether the read data is stored in a data storage circuit; and

wherein the outputting selectively outputs one of corrected data and second data from the memory cell based on the data storage status indicator.