PHOTODIODE WITH DIFFERENT ELECTRIC POTENTIAL REGIONS FOR IMAGE SENSORS

• US 20140246568A1
• Filed: 03/04/2013
• Published: 09/04/2014
• Est. Priority Date: 03/04/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wan, Chung Chun
• Granted Patent: US 9,276,031 B2
• Time in Patent Office: Days
• US Class Current: 250/214.1
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 23/54 Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

An image sensor pixel is disclosed. The pixel may include a photodiode having a first region with a first potential and a second region with a second, higher potential, with the second region being offset in depth from the first region in a semiconductor chip. A storage node may be positioned at substantially the same depth as the second region of the photodiode. A storage gate may be operable to transfer charge between the photodiode and the storage node.

Claims

1. An image sensor pixel, comprising:

a photodiode having a first region with a first potential and a second region with a second, higher potential, the second region offset in depth from the first region in a semiconductor chip;

a storage node positioned at substantially the same depth as the second region of the photodiode; and

a storage gate operable to selectively transfer charge from the photodiode to the storage node.

2. The image sensor pixel of claim 1, wherein the first region is doped with a first concentration of dopant and the second region is doped with a second concentration of dopant, the second concentration being greater than the first concentration.

3. The image sensor pixel of claim 2, wherein the dopant is n-type.

4. The image sensor pixel of claim 1, wherein the photodiode substantially extends between first and second surfaces of the semiconductor chip and the storage node is positioned proximate the second surface of the semiconductor chip beneath at least a portion of the first region of the photodiode.

5. The image sensor pixel of claim 4, wherein the photodiode is pinned at both the first and second surfaces of the semiconductor chip.

6. The image sensor pixel of claim 1, wherein the storage node is a first storage node, and further comprising a second storage node positioned at substantially the same depth as the second region of the photodiode.

7. The image sensor pixel of claim 1, wherein the thickness in depth of the second region of the photodiode is less than the thickness in depth of the storage node.

8. The image sensor pixel of claim 1, further comprising a shielded region coupled between the first region of the photodiode and the storage node.

9. The image sensor pixel of claim 8, wherein the shielded region is operable to electrically shield the storage node.

10. The image sensor pixel of claim 8, wherein the shielded region is operable to optically shield the storage node.

11. The image sensor pixel of claim 1, wherein the storage gate is coupled to the second region and is configured to selectively increase the potential of the second region in response to an applied voltage.

12. The image sensor pixel of claim 1, wherein the storage gate is coupled between the photodiode and the storage node and is configured to form a channel between the photodiode and the storage node responsive to an applied voltage.

13. The image sensor pixel of claim 1, wherein the photodiode further comprises a transition region between the first and second regions, and a potential of the transition region gradually increases from the first region to the second region.

14. A method of operating an image sensor pixel, comprising:

integrating charge in a first region of a photodiode;

funneling charge from the first region of the photodiode to a second region of the photodiode responsive to a potential difference between the first and second regions; and

transferring charge from the second region of the photodiode to a storage node positioned at least partially beneath the first region of the photodiode.

15. The method of claim 14, wherein charge is funneled to the second region in response to a voltage applied to a storage gate.

16. The method of claim 14, wherein charge is transferred from the second region of the photodiode to the storage node in response to a voltage applied to a storage gate.

17. The method of claim 14, wherein the second region of the photodiode is offset in depth in a semiconductor chip from the first region.

18. A method of manufacturing an image sensor pixel, comprising:

forming a storage node and a second region of a photodiode on a second surface of a silicon wafer; and

forming a first region of the photodiode on a first surface of the silicon wafer, the first region of the photodiode having a lower concentration of doping than the second region, and the first region of the photodiode at least partially covering the storage node formed on the second surface of the silicon wafer.

19. The method of claim 18, further comprising pinning the second region of the photodiode to the second surface of the silicon wafer and pinning the first region of the photodiode to the first surface of the silicon wafer.

20. The method of claim 18, further comprising forming a plurality of first regions of photodiodes on the first surface of the silicon wafer by blanket implants.