SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

• US 20140246718A1
• Filed: 05/15/2014
• Published: 09/04/2014
• Est. Priority Date: 04/12/2011
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: TAKETANI, Eiichi, OOSAWA, Seigo
• Granted Patent: US 9,171,906 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.

Claims

1. A manufacturing method of a semiconductor device, comprising:

preparing a semiconductor substrate having a main surface and including a drift layer of a first conductivity type;

defining a trench in the semiconductor substrate from the main surface into the drift layer;

forming an adjustment layer at a portion of the semiconductor substrate adjacent to a bottom wall of the trench, the adjustment layer having a first conductivity type impurity concentration higher than the drift layer;

forming a gate insulating layer covering a sidewall and the bottom wall of the trench;

forming a channel layer by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to the sidewall of the trench and between the adjustment layer and the main surface while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer; and

embedding a gate electrode in the trench after the forming the gate insulating layer.

2. The manufacturing method according to claim 1,

wherein the forming the channel layer includes implanting the second conductivity type impurities obliquely to the sidewall of the trench.

3. The manufacturing method according to claim 1,

wherein the forming the channel layer is performed after the forming the gate insulating layer, and

wherein the forming the gate insulating layer includes forming the gate insulating layer in such a manner that a thickness of the gate insulating layer formed on the bottom wall of the trench is larger than a thickness of the gate insulating layer formed on the sidewall of the trench.

4. The manufacturing method according to claim 1,

wherein the forming the gate insulating layer includes:

forming a sidewall insulating layer on the sidewall of the trench, and

forming a bottom wall insulating layer thicker than the sidewall insulating layer by selectively oxidizing the bottom wall of the trench, and

wherein the forming the channel layer includes introducing the second conductivity type impurities using the bottom wall insulating layer as a mask.

5. The manufacturing method according to claim 4,

wherein the forming the bottom wall insulating layer includes:

depositing a nitride layer to a whole area of the main surface of the semiconductor substrate after the forming the sidewall insulating layer;

selectively removing the nitride layer formed on the bottom wall of the trench while leaving the nitride layer formed on the sidewall of the trench by anisotropic etching in a depth direction of the trench; and

selectively oxidizing the bottom wall of the trench, from which the nitride layer is removed, by thermally oxidizing the semiconductor substrate.

6. The manufacturing method according to claim 4,

wherein the forming the bottom wall insulating layer includes selectively oxidizing the bottom wall of the trench by introducing oxygen plasma in a depth direction of the trench.

7. The manufacturing method according to claim 1,

wherein the forming the gate electrode includes forming the gate electrode in such a manner that an end portion of the gate electrode adjacent to the main surface is located at a position in the trench deeper than an open end of the trench, and

the manufacturing method further comprising forming a source layer or an emitter layer by implanting first conductivity type impurities at least from the sidewall of the trench after the forming the gate electrode.

8. The manufacturing method according to claim 1, further comprising

forming a high concentration body region at a portion of the semiconductor substrate adjacent to the channel layer,

wherein the high concentration body region has a second conductivity type impurity concentration higher than the channel layer.

9. The manufacturing method according to claim 8,

wherein the forming the high concentration body region includes performing ion implantation in a plurality of steps with different implantation depths.

10. The manufacturing method according to claim 8,

wherein the forming the high concentration body region includes:

defining another trench above a portion where the high concentration body region is to be formed; and

performing ion implantation through the another trench.

11. The manufacturing method according to claim 1, further comprising

forming a low concentration body layer by introducing second conductivity type impurities from the main surface of the semiconductor substrate before the defining the trench,

wherein the forming channel layer includes forming the channel layer along the sidewall of the trench,

wherein the low concentration body layer has a second conductivity type impurity concentration lower than the channel layer, and

wherein the low concentration body layer is shallower than a depth of the trench.

12. The manufacturing method according to claim 11, wherein

the defining the trench includes using an etchant with which an etching rate of the drift layer is lower than an etching rate of the low concentration body layer.

13. A manufacturing method of a semiconductor device, comprising:

preparing a semiconductor substrate having a main surface and including a drift layer of a first conductivity type;

defining a trench in the semiconductor substrate from the main surface into the drift layer;

forming a channel layer shallower than the trench by implanting second conductivity type impurities from the main surface of the semiconductor substrate before or after the defining the trench;

forming an adjustment layer at a portion of the semiconductor substrate located on a bottom wall of the trench and adjacent to the channel layer by introducing first conductivity type impurities at a higher concentration than the drift layer;

forming a gate insulating layer covering a sidewall and the bottom wall of the trench;

embedding a gate electrode in the trench after the forming the gate insulating layer, wherein

the adjustment layer restricts the channel layer from extending in a depth direction of the trench.

14-16. -16. (canceled)

17. A manufacturing method of a semiconductor device, comprising:

preparing a semiconductor substrate having a main surface and including a drift layer of a first conductivity type;

defining a trench in the semiconductor substrate from the main surface into the drift layer;

forming a gate insulating layer covering a sidewall and a bottom wall of the trench, the forming the gate insulating layer including forming a sidewall insulating layer on a sidewall of the trench and forming a bottom wall insulating layer thicker than the sidewall insulating layer on a bottom wall of the trench by selectively oxidizing the bottom wall of the trench after the forming the sidewall insulating layer;

forming a channel layer along the sidewall of the trench by introducing second conductivity type impurities from the sidewall of the trench using the bottom wall insulating layer as a mask; and

embedding a gate electrode in the trench after the forming the gate insulating layer.

18. The manufacturing method according to claim 17,

wherein the forming the bottom wall insulating layer includes:

depositing a nitride layer to a whole area of the main surface of the semiconductor substrate after the forming the sidewall insulating layer;

selectively removing the nitride layer formed on the bottom wall of the trench while leaving the nitride layer formed on the sidewall of the trench by anisotropic etching in a depth direction of the trench; and

selectively oxidizing the bottom wall of the trench, from which the nitride layer is removed, by thermally oxidizing the semiconductor substrate.

19. The manufacturing method according to claim 17,

wherein the forming the bottom wall insulating layer includes selectively oxidizing the bottom wall of the trench by introducing oxygen plasma in a depth direction of the trench.

20. The manufacturing method according to claim 17,

wherein the forming the channel layer includes implanting the second conductivity type impurities obliquely to the sidewall of the trench.

21. The manufacturing method according to claim 17, further comprising

forming a low concentration body layer by introducing second conductivity type impurities from the main surface of the semiconductor substrate before the defining the trench,

wherein the low concentration body layer has an impurity concentration lower than the channel layer, and

wherein the low concentration body layer is shallower than the trench.

22. The manufacturing method according to claim 21, wherein

the defining the trench includes using an etchant with which an etching rate of the drift layer is lower than an etching rate of the low concentration body layer.

23. The manufacturing method according to claim 17, further comprising

forming a high concentration body region at a portion of the semiconductor substrate adjacent to the channel layer after the forming the channel layer,

wherein the high concentration body region has a second conductivity type impurity concentration higher than the channel layer.

24. The manufacturing method according to claim 23,

wherein the forming the high concentration body region includes forming the high concentration body region to a depth similar to a lower end portion of the channel layer.

25. The manufacturing method according to claim 23,

wherein the forming the high concentration body region includes performing ion implantation in a plurality of steps with different implantation depths.

26. The manufacturing method according to claim 23,

wherein the forming the high concentration body region includes:

defining another trench above a portion where the high concentration body region is to be formed; and

performing ion implantation through the another trench.

27. The manufacturing method according to claim 17,

wherein the forming the gate electrode includes forming the gate electrode in such a manner that an end portion of the gate electrode adjacent to the main surface is located at a portion in the trench deeper than an open end of the trench, and

the manufacturing method further comprising forming a source layer or an emitter layer by implanting first conductivity type impurities at least from the sidewall of the trench after the forming the gate electrode.