CONVERTERS
First Claim
Patent Images
1. A converter comprising:
- a bridge comprising;
an AC terminal for each of at least one AC line;
a first DC terminal and a second DC terminal;
a first converter arm connected between each respective AC terminal and the first DC terminal; and
a second converter arm connected between each respective AC terminal and the second DC terminal, each converter arm comprising at least one first power semiconductor switching device configured to be turned ‘
on’ and
‘
off’
by gate control, and have a recovery time,wherein the converter is configured to operate in at least one of the following inverting modes;
(a) a first naturally commutated inverting mode wherein, during each commutation event, an incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in an outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor device is turned ‘
off’
by gate control at the reference time, and the available circuit commutated turn-off time is greater than the recovery time that is applicable with an open circuit gate terminal bias applied,(b) a second naturally commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘
off’
by gate control at the reference time, and the available circuit commutated turn-off time is shorter than the recovery time that is applicable with an open circuit gate terminal bias applied, the available circuit commutated turn-off time optionally being zero or close to zero, and(c) a combined naturally commutated and gate commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘
off’
by gate control at the reference time or at a point in time that is delayed beyond the reference time, and the available circuit commutated turn-off time is less than zero.
1 Assignment
0 Petitions
Accused Products
Abstract
A converter, and in particular a current source converter, including a bridge having an AC terminal for each of one or more AC lines, and first and second DC terminals. A converter arm is connected between each respective AC terminal and the first DC terminal, and between each respective AC terminal and the second DC terminal. Each converter arm includes a first power semiconductor switching device capable of being turned ‘on’ and ‘off’ by gate control and having a recovery time. The converter is adapted to be operated in one or more inverting modes.
-
Citations
20 Claims
-
1. A converter comprising:
-
a bridge comprising; an AC terminal for each of at least one AC line; a first DC terminal and a second DC terminal; a first converter arm connected between each respective AC terminal and the first DC terminal; and a second converter arm connected between each respective AC terminal and the second DC terminal, each converter arm comprising at least one first power semiconductor switching device configured to be turned ‘
on’ and
‘
off’
by gate control, and have a recovery time,wherein the converter is configured to operate in at least one of the following inverting modes; (a) a first naturally commutated inverting mode wherein, during each commutation event, an incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in an outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor device is turned ‘
off’
by gate control at the reference time, and the available circuit commutated turn-off time is greater than the recovery time that is applicable with an open circuit gate terminal bias applied,(b) a second naturally commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘
off’
by gate control at the reference time, and the available circuit commutated turn-off time is shorter than the recovery time that is applicable with an open circuit gate terminal bias applied, the available circuit commutated turn-off time optionally being zero or close to zero, and(c) a combined naturally commutated and gate commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘
off’
by gate control at the reference time or at a point in time that is delayed beyond the reference time, and the available circuit commutated turn-off time is less than zero. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. An arrangement comprising:
-
a converter comprising; a bridge comprising; an AC terminal for each of at least one AC line; a first DC terminal and a second DC terminal; a first converter arm connected between each respective AC terminal and the first DC terminal; and a second converter arm connected between each respective AC terminal and the second DC terminal, wherein each converter arm comprises at least one first power semiconductor switching device configured to be turned ‘
on’ and
‘
off’
by gate control, and have a recovery time;an AC grid; and a DC link, wherein the converter is configured to operate in at least one of the following inverting modes; (a) a first naturally commutated inverting mode wherein, during each commutation event, an incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in an outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor device is turned ‘
off’
by gate control at the reference time, and the available circuit commutated turn-off time is greater than the recovery time that is applicable with an open circuit gate terminal bias applied,(b) a second naturally commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘
off’
by gate control at the reference time, and the available circuit commutated turn-off time is shorter than the recovery time that is applicable with an open circuit gate terminal bias applied, the available circuit commutated turn-off time optionally being zero or close to zero, and(c) a combined naturally commutated and gate commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘
off’
by gate control at the reference time or at a point in time that is delayed beyond the reference time, and the available circuit commutated turn-off time is less than zero,wherein the at least one AC line of the converter is connected to the AC grid, and the DC terminals of the converter are connected to the DC link. - View Dependent Claims (15, 16, 17, 18, 19)
-
-
20. An arrangement comprising:
-
a plurality of converters, each of the plurality of converters comprising, a bridge comprising; an AC terminal for each of at least one AC line; a first DC terminal and a second DC terminal; a first converter arm connected between each respective AC terminal and the first DC terminal; and a second converter arm connected between each respective AC terminal and the second DC terminal, wherein each converter arm comprises at least one first power semiconductor switching device configured to be turned ‘
on’ and
‘
off’
by gate control, and have a recovery time,wherein the converter is configured to operate in at least one of the following inverting modes; (a) a first naturally commutated inverting mode wherein, during each commutation event, an incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in an outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor device is turned ‘
off’
by gate control at the reference time, and the available circuit commutated turn-off time is greater than the recovery time that is applicable with an open circuit gate terminal bias applied,(b) a second naturally commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘
off’
by gate control at the reference time, and the available circuit commutated turn-off time is shorter than the recovery time that is applicable with an open circuit gate terminal bias applied, the available circuit commutated turn-off time optionally being zero or close to zero, and(c) a combined naturally commutated and gate commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘
on’
by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘
off’
by gate control at the reference time or at a point in time that is delayed beyond the reference time, and the available circuit commutated turn-off time is less than zero,wherein the first and the second DC terminals of the plurality of converters are connected in parallel.
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeGE Energy Power Conversion Technology Limited (GE Vernova, Inc.)
-
Original AssigneeGE Energy Power Conversion Technology Limited (GE Vernova, Inc.)
-
InventorsCrane, Allan David, Blewitt, Warren Mark
-
Granted Patent
-
Time in Patent OfficeDays
-
Field of Search
-
US Class Current363/35
-
CPC Class CodesH02J 3/36 Arrangements for transfer o...H02M 1/08 Circuits specially adapted ...H02M 7/5152 with separate extinguishing...H02M 7/521 in a bridge configuration
