STRESS MEMORIZATION TECHNIQUE
First Claim
1. A method, comprising:
- providing a semiconductor structure comprising a gate structure provided over a semiconductor region;
performing an ion implantation process that amorphizes a first portion of said semiconductor region adjacent said gate structure and a second portion of said semiconductor region adjacent said gate structure so that a first amorphized region and a second amorphized region are formed adjacent said gate structure; and
performing an atomic layer deposition process that deposits a layer of a material having an intrinsic stress over said semiconductor structure, a temperature at which at least a part of said atomic layer deposition process is performed and a duration of said at least a part of said atomic layer deposition process being selected such that said first amorphized region and said second amorphized region re-crystallize during said atomic layer deposition process.
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Accused Products
Abstract
A method comprises providing a semiconductor structure comprising a gate structure provided over a semiconductor region. An ion implantation process is performed. In the ion implantation process, a first portion of the semiconductor region adjacent the gate structure and a second portion of the semiconductor region adjacent the gate structure are amorphized so that a first amorphized region and a second amorphized region are formed adjacent the gate structure. An atomic layer deposition process is performed. The atomic layer deposition process deposits a layer of a material having an intrinsic stress over the semiconductor structure. A temperature at which at least a part of the atomic layer deposition process is performed and a duration of the at least a part of the atomic layer deposition process are selected such that the first amorphized region and the second amorphized region are re-crystallized during the atomic layer deposition process.
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Citations
21 Claims
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1. A method, comprising:
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providing a semiconductor structure comprising a gate structure provided over a semiconductor region; performing an ion implantation process that amorphizes a first portion of said semiconductor region adjacent said gate structure and a second portion of said semiconductor region adjacent said gate structure so that a first amorphized region and a second amorphized region are formed adjacent said gate structure; and performing an atomic layer deposition process that deposits a layer of a material having an intrinsic stress over said semiconductor structure, a temperature at which at least a part of said atomic layer deposition process is performed and a duration of said at least a part of said atomic layer deposition process being selected such that said first amorphized region and said second amorphized region re-crystallize during said atomic layer deposition process. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method, comprising:
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providing a semiconductor structure, said semiconductor structure comprising; a first transistor element, said first transistor element comprising a first gate structure provided on a first semiconductor region; and a second transistor element, said second transistor element comprising a second gate structure provided on a second semiconductor region; the method further comprising; forming a first amorphized region in said first semiconductor region adjacent said first gate structure and a second amorphized region in said first semiconductor region adjacent said first gate structure, wherein no amorphized region is formed in said second semiconductor region; and performing an atomic layer deposition process that deposits a layer of a material having an intrinsic stress above said first semiconductor region and said second semiconductor region, a temperature at which at least a part of said atomic layer deposition process is performed and a duration of said at least a part of said atomic layer deposition process being selected such that said first amorphized region and said second amorphized region re-crystallize substantially completely during said atomic layer deposition process. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification