STRESS MEMORIZATION TECHNIQUE

• US 20140248749A1
• Filed: 03/04/2013
• Published: 09/04/2014
• Est. Priority Date: 03/04/2013
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Hoentschel, Jan, Flachowsky, Stefan, Sassiat, Nicolas, Richter, Ralf
• Application Number:
  US13/783,685
• Publication Number:
  US 20140248749A1
• Time in Patent Office: Days
• US Class Current: 438/231
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

A method comprises providing a semiconductor structure comprising a gate structure provided over a semiconductor region. An ion implantation process is performed. In the ion implantation process, a first portion of the semiconductor region adjacent the gate structure and a second portion of the semiconductor region adjacent the gate structure are amorphized so that a first amorphized region and a second amorphized region are formed adjacent the gate structure. An atomic layer deposition process is performed. The atomic layer deposition process deposits a layer of a material having an intrinsic stress over the semiconductor structure. A temperature at which at least a part of the atomic layer deposition process is performed and a duration of the at least a part of the atomic layer deposition process are selected such that the first amorphized region and the second amorphized region are re-crystallized during the atomic layer deposition process.

Claims

1. A method, comprising:

providing a semiconductor structure comprising a gate structure provided over a semiconductor region;

performing an ion implantation process that amorphizes a first portion of said semiconductor region adjacent said gate structure and a second portion of said semiconductor region adjacent said gate structure so that a first amorphized region and a second amorphized region are formed adjacent said gate structure; and

performing an atomic layer deposition process that deposits a layer of a material having an intrinsic stress over said semiconductor structure, a temperature at which at least a part of said atomic layer deposition process is performed and a duration of said at least a part of said atomic layer deposition process being selected such that said first amorphized region and said second amorphized region re-crystallize during said atomic layer deposition process.

2. The method of claim 1, wherein said first and said second amorphized regions re-crystallize substantially completely during said atomic layer deposition process.

3. The method of claim 2, wherein the re-crystallization of said first and said second amorphized regions forms a first and a second stressed region adjacent said gate structure, said first and said second stressed regions having an intrinsic stress.

4. The method of claim 3, wherein the intrinsic stress of said layer of said material deposited by said atomic layer deposition process is a tensile stress, and wherein the intrinsic stress of said first and said second stressed regions is a tensile stress.

5. The method of claim 1, wherein said at least a part of said atomic layer deposition process is performed at a temperature that is greater than at least one of 500°

C. and 550°

C.

6. The method of claim 5, wherein said at least a part of said atomic layer deposition process is performed at a temperature in at least one of a range from about 500-700°

C., a range from about 500-600°

C. and a range from about 550-600°

C.

7. The method of claim 6, wherein the temperature at which said atomic layer deposition process is performed is maintained substantially constant during said atomic layer deposition process, and a duration of said atomic layer deposition process is in a range from about one hour to about seven hours.

8. The method of claim 1, wherein said layer of said material deposited by said atomic layer deposition process comprises silicon nitride.

9. The method of claim 8, wherein said atomic layer deposition process comprises alternately supplying a first precursor comprising silicon and a second precursor comprising nitrogen to a surface of said semiconductor structure, wherein said first precursor comprises at least one of monochlorosilane, dichlorosilane, trichlorosilane and tetrachlorosilane, and wherein said second precursor comprises at least one of ammonia and hydrazine.

10. The method of claim 1, wherein said ion implantation process comprises irradiating said semiconductor structure with ions of at least one of a noble gas and an element from the carbon group of the periodic table of elements.

11. The method of claim 10, wherein said ion implantation process additionally comprises irradiating said semiconductor structure with ions of at least one of fluorine and nitrogen.

12. The method of claim 1, wherein said gate structure comprises:

a gate electrode provided above said semiconductor region;

a gate insulation layer provided between said semiconductor region and said gate electrode; and

a first sidewall spacer formed at sidewalls of said gate electrode.

13. The method of claim 12, wherein said gate insulation layer comprises a high-k material having a dielectric constant greater than a dielectric constant of silicon dioxide, and said gate electrode comprises a metal.

14. The method of claim 12, further comprising:

before performing said atomic layer deposition process, forming an extended source region and an extended drain region adjacent said gate structure, the formation of said extended source region and said extended drain region comprising implanting ions of a dopant material; and

after performing said atomic layer deposition process, performing an anisotropic etch process, said anisotropic etch process forming a second sidewall spacer at sidewalls of the gate structure from said layer of said material deposited in said atomic layer deposition process and forming a source region and a drain region adjacent said gate structure, the formation of said source region and said drain region comprising implanting ions of a dopant material into said semiconductor region.

15. The method of claim 1, wherein the temperature at which said atomic layer deposition process is performed is increased during said atomic layer deposition process.

16. A method, comprising:

providing a semiconductor structure, said semiconductor structure comprising;

a first transistor element, said first transistor element comprising a first gate structure provided on a first semiconductor region; and

a second transistor element, said second transistor element comprising a second gate structure provided on a second semiconductor region;

the method further comprising;

forming a first amorphized region in said first semiconductor region adjacent said first gate structure and a second amorphized region in said first semiconductor region adjacent said first gate structure, wherein no amorphized region is formed in said second semiconductor region; and

performing an atomic layer deposition process that deposits a layer of a material having an intrinsic stress above said first semiconductor region and said second semiconductor region, a temperature at which at least a part of said atomic layer deposition process is performed and a duration of said at least a part of said atomic layer deposition process being selected such that said first amorphized region and said second amorphized region re-crystallize substantially completely during said atomic layer deposition process.

17. The method of claim 16, wherein the formation of said first amorphized region and said second amorphized region comprises performing an ion implantation process wherein ions of at least one of a noble gas and an element from the carbon group of the periodic table of elements are implanted into said first semiconductor region.

18. The method of claim 17, wherein said second semiconductor region comprises a stress-creating layer of silicon/germanium formed on silicon.

19. The method of claim 18, wherein:

said first gate structure comprises a first gate insulation layer comprising a high-k material having a dielectric constant that is greater than a dielectric constant of silicon dioxide, a first gate electrode comprising a first metal and a first sidewall spacer;

said second gate structure comprises a second gate insulation layer comprising a high k material having a dielectric constant that is greater than a dielectric constant of silicon dioxide, a second gate electrode comprising a second metal and a second sidewall spacer;

the method further comprises;

before performing said atomic layer deposition process, selectively implanting ions of an N-type dopant into said first semiconductor region to form a first source extension region and a first drain extension region adjacent said first gate structure and selectively implanting ions of a P-type dopant into said second semiconductor region to form a second source extension region and a second drain extension region adjacent said second gate structure; and

after performing said atomic layer deposition process, performing an anisotropic etch process to form from said layer of said material deposited in said atomic layer deposition process a third sidewall spacer at said first gate structure and a fourth sidewall spacer at said second gate structure, selectively implanting ions of an N-type dopant into said first semiconductor region to form a first source region and a first drain region adjacent said first gate structure and selectively implanting ions of a P-type dopant into said second semiconductor region to form a second source region and a second drain region adjacent said second gate structure.

20. The method of claim 19, wherein the formation of said first amorphized region and said second amorphized region additionally comprises implanting ions of at least one of fluorine and nitrogen into said first semiconductor region.

21. The method of claim 20, wherein the temperature at which said atomic layer deposition process is performed is increased during said atomic layer deposition process.