APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

• US 20140250279A1
• Filed: 03/04/2013
• Published: 09/04/2014
• Est. Priority Date: 03/04/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Granted Patent: US 9,158,667 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Claims

1. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array and configured to;

perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input; and

wherein the sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

2. The apparatus of claim 1, wherein the sensing circuitry is further configured to perform the logical operation and to store a result without enabling a local input/output (I/O) line coupled to the sensing circuitry.

3. The apparatus of claim 1, wherein the sensing circuitry is further configured to perform a number of subsequent logical operations using data values stored in the array as inputs and to store results of the number of subsequent operations in the array without transferring data via a sense line address access.

4. The apparatus of claim 1, wherein the sense line comprises a first sense line of a pair of complementary sense lines, and wherein the sensing circuitry comprises:

a sense amplifier coupled to the pair of complementary sense lines; and

a compute component coupled to the sense amplifier and comprising;

a cross coupled latch;

a pass transistor coupled to the cross coupled latch and to the first sense line; and

a pass transistor coupled to the cross coupled latch and to a second sense line of the pair of complementary sense lines.

5. The apparatus of claim 4, wherein transistors of the compute component are formed on pitch with memory cells of the array and/or with transistors of the sense amplifier.

6. The apparatus of claim 4, wherein the compute component further comprises:

an inverting transistor coupled to the cross coupled latch and to the first sense line; and

an inverting transistor coupled to the cross coupled latch and to the second sense line.

7. The apparatus of claim 6, wherein the cross coupled latch comprises a pair of n-channel transistors and a pair of p-channel transistors, and wherein:

a gate of a first of the pair of n-channel transistors and a gate of a first of the pair of p-channel transistors is coupled to a gate of the inverting transistor coupled to the cross coupled latch and to the first sense line; and

a gate of a second of the pair of n-channel transistors and a gate of a second of the pair of p-channel transistors is coupled to a gate of the inverting transistor coupled to the cross coupled latch and to the second sense line.

8. The apparatus of claim 6, wherein the sensing circuitry is configured to perform at least one of an AND operation, a NAND operation, and an invert operation responsive to particular control signals applied to at least one of the compute component and the sense amplifier.

9. The apparatus of claim 1, wherein the sensing circuitry is configured to perform the logical operation and store the result using an amount of energy less than an amount of energy needed to charge a sense line of the array from a ground voltage to a supply voltage corresponding to the array.

10. The apparatus of claim 1, wherein the array of memory cells comprises 1 transistor 1 capacitor (1T1C) memory cells.

11. The apparatus of claim 1, wherein the sensing circuitry is configured to store a result of the logical operation in at least one of the first memory cell and the second memory cell without transferring data via a sense line address access.

12. The apparatus of claim 1, wherein the sensing circuitry is configured to store a result of the logical operation in a third memory cell coupled to the sense line without transferring data via a sense line address access.

13. The apparatus of claim 12, wherein the third memory cell is either the first memory cell or the second memory cell, and wherein storing the result of the logical operation in the third memory cell comprises overwriting data stored in either the first memory cell or the second memory cell.

14. The apparatus of claim 1, wherein at least one of the first memory cell and the second memory cell are destructive read memory cells.

15. A method, comprising:

determining data values stored in a number of memory cells of a first row of an array of memory cells, each of the number of memory cells coupled to a respective sense line of a number of sense lines; and

performing, in parallel, logical operations using the data values stored in the number of memory cells of the first row as a number of first inputs and data values stored in a number of memory cells of a second row of the array as a number of second inputs, wherein each of the number of memory cells of the second row are coupled to a respective sense line of the number of sense lines; and

wherein the logical operations are performed in parallel without transferring data via a bus.

16. The method of claim 15, further comprising storing results of the logical operations in the array.

17. The method of claim 15, wherein:

each of the number of sense lines is coupled to a respective sense amplifier of a number of sense amplifiers;

each of the number of sense amplifiers is coupled to a respective cross coupled latch of a number of cross coupled latches, wherein each of the number of cross coupled latches comprises a pair of n-channel transistors, a pair of p-channel transistors, a pair of pass transistors, and a pair of inverting transistors; and

wherein performing the logical operations comprises;

transferring the data values stored in the number of memory cells of the first row to the number of cross coupled latches during a first operation phase in which the pass transistors are enabled;

determining the data values stored in the number of memory cells of the second row while the pass transistors are disabled; and

subsequently enabling only one respective pass transistor of each of the pair of pass transistors such that each cross coupled latch of the number of cross coupled latches stores a respective data value corresponding to an AND of a data value stored in a respective memory cell of the number of memory cells of the first row and a data value stored in a respective memory cell of the number of memory cells of the second row.

18. The method of claim 17, wherein performing the logical operations further comprises enabling the inverting transistors such that each cross coupled latch of the number of cross coupled latches stores a respective data value corresponding to a NAND of a data value stored in a respective memory cell of the number of memory cells of the first row and a data value stored in a respective memory cell of the number of memory cells of the second row.

19. A method, comprising:

storing data corresponding to a first input and a second input in an array of memory cells;

performing a logical operation using the first input and the second input, and

storing a result of the logical operation in the array;

wherein the logical operation is performed and the result is stored in the array without transferring data via a sense line address access.

20. The method of claim 19, wherein an amount of energy about equal to an amount of energy used to charge a sense line of the array to a voltage of about one half of a supply voltage corresponding to the array is expended in order to store the result of the logical operation in the array.

21. The method of claim 19, wherein storing data corresponding to the first input and the second input comprises storing the data corresponding to the first input in a first row of the array and storing the data corresponding to the second input in a second row of the array;

wherein storing the result of the logical operation in the array comprises storing the result in a third row of the array.

22. The method of claim 19, wherein performing the logical operation comprises:

determining a data value stored in a memory cell;

copying the determined data value into a cross coupled latch through an enabled first pass transistor coupled to a sense line corresponding to the memory cell and an enabled second pass transistor coupled to a complementary sense line corresponding to the memory cell;

performing at least one of an AND, OR, NAND, and NOR logical operation by subsequently performing a number of operation phases during which only one of the first pass transistor and the second pass transistor is enabled.

23. The method of claim 22, wherein performing the logical operation further comprises accumulating a result of the number of operation phases in the cross coupled latch, and wherein storing the result of the logical operation comprises transferring the result of the number of operation phases from the cross coupled latch to a different memory cell.

24. The method of claim 19, wherein performing the logical operation comprises performing a NAND operation.

25. The method of claim 19, wherein performing the logical operation comprises transferring, from a secondary latch to a primary latch, a data value stored in the secondary latch, and wherein storing the result comprises overwriting a data value stored in a particular row of the array with the data value transferred to the primary latch.

26. The method of claim 19, wherein storing the result of the logical operation in the array comprises storing the result in a memory cell from which the data corresponding to at least one of the first input and the second input was read.

31. The apparatus of claim 23, wherein the processing resource is configured to perform a logical operation in addition to the logical operation performed using the data on the pair of complementary sense lines.

27. An apparatus, comprising:

an array of memory cells;

a controller coupled to the array and configured to;

apply control signals to sensing circuitry coupled to the array to perform a logical operation using data on a pair of complementary sense lines as inputs of the logical operation; and

apply control signals to the sensing circuitry to store a result of the logical operation in the array without transferring data via local input/output (I/O) lines coupled to the sensing circuitry.

28. The apparatus of claim 27, further comprising a processing resource coupled to the controller.

29. The apparatus of claim 28, wherein the controller is located on a same chip as the array and is couple thereto via an I/O bus, and wherein the processing resource comprises a processor external to the same chip.

30. The apparatus of claim 28, wherein the controller is located on a same chip as the array and is coupled thereto via an I/O bus, and wherein the processing resource comprises a processor located on the same chip.

32. An apparatus, comprising:

a sense amplifier coupled to a pair of complementary sense lines of an array of memory cells; and

an accumulator coupled to the sense amplifier, the accumulator comprising;

a first pass transistor having a first source/drain region coupled to a first sense line of the pair of complementary sense lines;

a second pass transistor having a first source/drain region coupled to a second sense line of the pair of complementary sense lines;

a first pair of cross coupled transistors and a second pair of cross coupled transistors; and

wherein the apparatus is configured to perform a logical operation that comprises performing an accumulate operation on a data value represented by a signal on at least one of the pair of complementary sense lines.

33. The apparatus of claim 32, wherein:

a second source/drain region of the second pass transistor is commonly coupled to a gate of a first transistor of the first pair of cross coupled transistors, a gate of a first transistor of the second pair of cross coupled transistors, and a first source/drain region of a second transistor of the first pair of cross coupled transistors; and

a second source/drain region of the first pass transistor is commonly coupled to a gate of the second transistor of the first pair of cross coupled transistors, a gate of a second transistor of the second pair of cross coupled transistors, and a first source/drain region of the first transistor of the first pair of cross coupled transistors.

34. The apparatus of claim 33, wherein the apparatus is configured to perform the accumulate operation by applying an active control signal to at least one of a gate of the first pass transistor and a gate of the second pass transistor while applying an active control signal to a second source/drain region of the first pair of cross coupled transistors and while applying an active control signal to a second source/drain region of the second pair of cross coupled transistors.

35. The apparatus of claim 33, wherein the apparatus further comprises:

a first pull down transistor having a gate coupled to the gate of the second transistor of the second pair of cross coupled transistors;

a second pull down transistor having a gate coupled to the gate of the first transistor second pair of cross coupled transistors;

a third pull down transistor having a source/drain region coupled the first pull down transistor and having a gate configured to receive an invert signal; and

a fourth pull down transistor having a source/drain region coupled to the second pull down transistor and having a gate configured to receive the invert signal; and

wherein activating the invert signal serves to invert a data value stored in the accumulator and drive a signal corresponding to the inverted data value onto one of the pair of complementary sense lines.

36. The apparatus of claim 32, wherein the apparatus is configured to:

drive a result of the logical operation from the accumulator to the pair of complementary sense lines through one of the first and the second pass transistor;

amplify the result via the sense amplifier; and

responsive to a read request, transfer the result from the sense amplifier via a pair of input/output lines without accessing data stored in the array.

37. The apparatus of claim 32, wherein the sense amplifier comprises a pair of cross coupled n-channel transistors, a pair of cross coupled p-channel transistors, and a number of equilibration transistors.

38. The apparatus of claim 32, wherein the apparatus is configured to perform the logical operation without transferring data from the array to the sense amplifier and without transferring data from the sense amplifier to the array.

39. The apparatus of claim 32, wherein the array of memory cells comprises a number of destructive read memory cells.

40. A method, comprising:

sensing a data value using a sense amplifier coupled to a pair of complementary sense lines corresponding to an array of memory cells;

performing a logic operation using the data value as an input, wherein performing the logic operation includes;

providing a first control signal to a first source/drain region of a first pair of cross coupled transistors of an accumulator;

providing a second control signal to a first source/drain region of a second pair of cross coupled transistors of the accumulator; and

while the first and second control signals are provided to the first source/drain regions of the respective first and second pairs of cross coupled transistors of the accumulator, providing at least one of;

a third control signal to a gate of a first pass transistor having a first source/drain region coupled to a first sense line of the pair of complementary sense lines and having a second source/drain region commonly coupled to a second source/drain region of a first transistor of the first pair of cross coupled transistors, a gate of a second transistor of the first pair of cross coupled transistors, and a gate of a second transistor of the second pair of cross coupled transistors; and

a fourth control signal to a gate of a second pass transistor having a first source/drain region coupled to a second sense line of the pair of complementary sense lines and having a second source/drain region commonly coupled to a second source/drain region of the second transistor of the first pair of cross coupled transistors, a gate of the first transistor of the first pair of cross coupled transistors, and a gate of a first transistor of the second pair of cross coupled transistors.

41. The method of claim 40, wherein the method includes sensing the data value without activating a row of the array.

42. The method of claim 40, wherein the data value comprises a first data value and wherein performing the logic operation further includes:

copying the first data value to the accumulator;

sensing a second data value using the sense amplifier, the second data value serving as a second input to the logic operation;

performing an accumulate function by activating only one of the first and the second pass transistors while the first and the second control signals are provided to the first source/drain regions of the respective first and second pairs of cross coupled transistors of the accumulator.

43. The method of claim 40, wherein the method includes providing a result of the logic operation to a location other than a memory cell of the array.

44. An apparatus, comprising:

a sense amplifier coupled to a pair of complementary sense lines of an array of memory cells; and

a compute component coupled to the sense amplifier and comprising;

a first pass transistor coupled to a first sense line of the pair of complementary sense lines and a second pass transistor coupled to a second sense line of the pair of complementary sense lines;

a first n-channel transistor of a pair of cross coupled n-channel transistors coupled to the first pass transistor and a second n-channel transistor of the pair of cross coupled n-channel transistors coupled to the second pass transistor;

a first p-channel transistor of a pair of cross coupled p-channel transistors coupled to the first pass transistor and a second p-channel transistor of the pair of cross coupled p-channel transistors coupled to the second pass transistor;

a first pull down transistor coupled to the first sense line and a second pull down transistor coupled to the second sense line;

a third pull down transistor coupled the first pull down transistor and to a gate of the second n-channel transistor, which is coupled to a gate of the second p-channel transistor; and

a fourth pull down transistor coupled to the second pull down transistor and to a gate of the first n-channel transistor, which is coupled to a gate of the first p-channel transistor.

45. The apparatus of claim 44, wherein the apparatus is configured to perform a logic operation responsive to control signals provided thereto.

46. The sensing circuit of claim 44, wherein the apparatus is configured to perform the logic operation without enabling a sense line decode signal used to transfer data values corresponding to the complementary sense lines to local input/output (I/O) lines.

47. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array and configured to perform a logical operation using a first data value on a sense line of the array coupled to the sensing circuitry at a first point in time as a first input and a second data value on the sense line at a second point in time as a second input; and

wherein the sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

48. The apparatus of claim 47, wherein the sensing circuitry comprises a sense amplifier and a compute component coupled to a column of the array.

49. The apparatus of claim 48, wherein the sense amplifier and/or compute component are configured to receive an input from another sense amplifier and/or another compute component, wherein the other sense amplifier and compute component are coupled to another column of memory cells.

50. The apparatus of claim 49, wherein the other column of memory cells is in the array.

51. The apparatus of claim 49, wherein the other column of memory cells in another array of memory cells.

52. The apparatus of claim 47, wherein the sensing circuitry is further configured to store a result of the logical operation in a memory cell coupled to the sense line.

53. The apparatus of claim 47, wherein the sensing circuitry is further configured to transfer a result of the logical operation external to the sensing circuitry and the array.

54. The apparatus of claim 47, wherein the sensing circuitry being configured to perform a logical operation comprises the sensing circuitry being configured to perform a Boolean operation.

55. The apparatus of claim 47, wherein the sensing circuitry being configured to perform a logical operation comprises the sensing circuitry being configured to perform a non-Boolean operation.

56. The apparatus of claim 47, wherein the sensing circuitry is configured to sense the first data value from a first memory cell coupled to the sense line and is configured to sense the second data value from a second memory cell coupled to the sense line.

57. The apparatus of claim 47, wherein the sensing circuitry is configured to provide the first data value and/or the second data value on the sense line from an I/O line coupled to the sensing circuitry.

58. The apparatus of claim 47, wherein the sensing circuitry is configured to provide the first data value and/or the second data value on the sense line from other sensing circuitry.

59. The apparatus of claim 47, wherein the sensing circuitry further comprises a sense amplifier configured to receive the first data value and/or the second data value from an I/O line coupled to the sense amplifier.

60. The apparatus of claim 47, wherein the sensing circuitry further comprises a sense amplifier configured to receive the first data value and/or the second data value from another sense amplifier coupled to the sense amplifier.

61. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array and configured to;

perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input; and

wherein the sensing circuitry is configured to perform the logical operation without enabling a local input/output (I/O) line coupled to the sensing circuitry.

62. The apparatus of claim 61, wherein the sense line comprises a first sense line of a pair of complementary sense lines, and wherein the sensing circuitry comprises:

a sense amplifier coupled to the pair of complementary sense lines; and

a compute component coupled to the sense amplifier and comprising;

a cross coupled latch;

a pass transistor coupled to the cross coupled latch and to the first sense line; and

a pass transistor coupled to the cross coupled latch and to a second sense line of the pair of complementary sense lines.