ANTI-TAMPER SYSTEM BASED ON DUAL RANDOM BITS GENERATORS FOR INTEGRATED CIRCUITS

• US 20140250541A1
• Filed: 02/21/2014
• Published: 09/04/2014
• Est. Priority Date: 03/01/2013
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: A/L KRISHNASAMY, Raj Kumar, THUM, Chia Chieh, LEE, Moo Kit
• Granted Patent: US 9,323,957 B2
• Time in Patent Office: Days
• US Class Current: 726/34
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/004 for fault attacks
• CPC Class Codes: H05K 1/0275 Security details, e.g. tampering prevention or detection

Abstract

An apparatus includes a mesh block, a first number generator configured to generate a first number, a second number generator configured to generate a second number, and a comparator block configured to compare the first number with the second number and generate an output signal from the mesh block. The output signal indicates an occurrence of an unauthorized activity on the mesh block.

Claims

1. A method comprising:

generating first and second numbers using first and second number generators in a mesh block, respectively; and

comparing the first number with the second number to generate an output signal from the mesh block,

wherein the output signal indicates an occurrence of an unauthorized activity on the mesh block.

2. The method of claim 1, wherein the first and second numbers are first and second pseudo-random numbers and are generated using first and second linear-feedback shift registers (LFSRs), respectively.

3. The method of claim 1, wherein the first and second numbers are first and second pseudo-random numbers and the first and second number generators are first and second pseudo-random number generators (PRNGs), respectively, and

wherein the method further comprises:

transmitting a first plurality of pseudo-random signals indicating the first pseudo-random number through a first plurality of mesh wires to a mesh buffer; and

converting the first plurality of pseudo-random signals into a plurality of modified signals using the mesh buffer.

4. The method of claim 3, wherein converting the first plurality of pseudo-random signals into the plurality of modified signals comprises:

inverting the first plurality of pseudo-random signals to generate the plurality of modified signals.

5. The method of claim 4, wherein comparing the first pseudo-random number with the second pseudo-random number comprises:

inverting the plurality of modified signals in a comparator to generate a first plurality of input signals, the first plurality of input signals having logic values corresponding to those of the first plurality of pseudo-random signals, respectively; and

comparing the first plurality of input signals with a second plurality of input signals from the second PRNG indicating the second pseudo-random number.

6. The method of claim 5, wherein comparing the first pseudo-random number with the second pseudo-random number further comprises comparing the first plurality of input signals with the second plurality of input signals in parallel.

7. The method of claim 3, further comprising:

outputting first one of the plurality of modified signals from the mesh buffer via first one of a second plurality of mesh wires extending from the mesh buffer; and

outputting second one of the plurality of modified signals from the mesh buffer via second one of the second plurality of mesh wires.

8. The method of claim 1, wherein the mesh block is a first mesh block and the output signal is a first output signal, the method further comprising:

generating third and fourth pseudo-random numbers using third and fourth PRNGs in a second mesh block, respectively;

comparing the third pseudo-random number with the fourth pseudo-random number to generate a second output signal from the second mesh block, wherein the second output signal indicates an occurrence of an unauthorized activity on the second mesh block; and

performing an OR operation on the first and second output signals in a clock tamper detector, the clock tamper detector producing a clock tamper detect signal.

9. The method of claim 8, further comprising:

setting the clock tamper detect signal to a logic value at a first time, and

setting the clock tamper detect signal to a result of the OR operation at a second time subsequent to the first time, the second time corresponding to a rising edge of a clock signal received by the clock tamper detector.

10. An apparatus comprising:

a mesh block;

a first number generator configured to generate a first number;

a second number generator configured to generate a second number; and

a comparator block configured to compare the first number with the second number and generate an output signal from the mesh block, the output signal indicating an occurrence of an unauthorized activity on the mesh block,

wherein the first number generator, the second number generator, and the comparator block are provided in the mesh block.

11. The apparatus of claim 10, wherein the first and second numbers are first and second pseudo-random numbers and are generated using first and second linear-feedback shift registers (LFSRs), respectively, and

wherein the second number generator is in the comparator block.

12. The apparatus of claim 10, wherein the first and second numbers are first and second pseudo-random numbers and the first and second number generators are first and second pseudo-random number generators (PRNGs), respectively, and

wherein the apparatus further comprises:

a first plurality of mesh wires configured to transmit a first plurality of pseudo-random signals indicating the first pseudo-random number;

a mesh buffer configured to convert the first plurality of pseudo-random signals into a plurality of modified signals; and

a second plurality of mesh wires configured to transmit the plurality of modified signals to the comparator block.

13. The apparatus of claim 12, wherein two neighboring wires among the first and second plurality of mesh wires are spaced about 0.4 μ

m apart from each other.

14. The apparatus of claim 12, wherein the mesh buffer includes:

a plurality of inverters configured to invert the first plurality of pseudo-random signals to generate the plurality of modified signals.

15. The apparatus of claim 14, wherein the comparator block includes:

an inverting block configured to invert the modified signals to generate a first plurality of input signals, the first plurality of input signals having logic values corresponding to those of the first plurality of pseudo-random signals, respectively; and

a comparator configured to compare the first plurality of input signals from the inverting block with a second plurality of input signals indicating the second pseudo-random number.

16. The apparatus of claim 15, wherein the comparator includes an iterative network having a plurality of cells, each cell receiving a first input signal among the first plurality of input signals and a second input signal among the second plurality of input signals, the first and second input signals indicating a pair of corresponding binary numbers.

17. The apparatus of claim 12, wherein the mesh buffer outputs first one of the plurality of modified signals via first one of the second plurality of mesh wires, and outputs second one of the plurality of modified signals via second one of the second plurality of mesh wires.

18. The apparatus of claim 10, wherein the mesh block is a first mesh block and the output signal is a first output signal, the apparatus further comprising:

a second mesh block configured to generate a second output signal, the second output signal indicating whether an unauthorized activity on the second mesh block is detected; and

a clock tamper detector that performs an OR operation on the first and second output signals and produces a clock tamper detect signal.

19. The apparatus of claim 18, wherein the clock tamper detector sets the clock tamper detect signal to have a logic value at a first time, and

the clock tamper detector sets the clock tamper detect signal to a result of the OR operation at a second time subsequent to the first time, the second time corresponding to a rising edge of a clock signal received by the clock tamper detector.

20. The apparatus of claim 10, wherein the first and second numbers are first and second pseudo-random numbers and are generated using first and second linear-feedback shift registers (LFSRs), respectively, and

wherein the mesh block includes:

a substrate;

a device layer disposed over the substrate and including a plurality of electronic devices;

a plurality of lower interconnection layers disposed over the device layer and including a plurality of wires interconnecting the plurality of electronic devices;

an upper interconnect layer disposed over the plurality of lower interconnection layers and including a plurality of wires, the plurality of wires configured to transmit a plurality of pseudo-random signals indicating the first pseudo-random number; and

a cover layer disposed over the upper interconnect layer,

wherein the plurality of lower interconnection layers includes;

a clock wire configured to provide a clock signal to the mesh block;

an alarm wire configured to transmit the output signal to a controller; and

a plurality of comparator block wires disposed in a comparator block and configured to transmit the plurality of pseudo-random signals to a comparator in the comparator block.