CHARGE TRANSFER IN IMAGE SENSORS

• US 20140252201A1
• Filed: 03/06/2013
• Published: 09/11/2014
• Est. Priority Date: 03/06/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Li, Xiangli, Fan, Xiaofeng, Wan, Chung Chun
• Granted Patent: US 9,741,754 B2
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H04N 25/587 acquired sequentially, e.g. using the combination of odd and even image fields
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

Apparatuses and methods for charge transfer in image sensors are disclosed. One example of an image sensor pixel may include a first charge storage node and a second charge storage node. A transfer circuit may be coupled between the first and second charge storage nodes, and the transfer circuit may have a first region proximate the first charge storage node and configured to have a first potential. The transfer circuit may also have a second region proximate the second charge storage node configured to have a second, higher potential. An input node may be configured to control the first and second potentials based on a transfer signal provided to the input node.

Claims

1. An image sensor pixel, comprising:

a first charge storage node;

a second charge storage node;

a transfer circuit coupled between the first and second charge storage nodes, the transfer circuit having a first region proximate the first charge storage node and configured to have a first potential, and a second region proximate the second charge storage node configured to have a second, higher potential; and

an input node configured to control the first and second potentials based on a transfer signal provided to the input node.

2. The image sensor pixel of claim 1, further comprising a virtual barrier coupled between the transfer circuit and the second charge storage node.

3. The image sensor pixel of claim 1, wherein the first charge storage node comprises a photodiode.

4. The image sensor pixel of claim 1, wherein the second charge storage node comprises a floating diffusion node.

5. The image sensor pixel of claim 1, wherein the image sensor comprises a stacked CMOS image sensor, with a photodiode on a first semiconductor chip and transfer circuitry on a second semiconductor chip stacked together with the first semiconductor chip, further wherein the first charge storage node is a stack contact on the second semiconductor chip and the second charge storage node is a global shutter storage node on the second semiconductor chip.

6. The image sensor pixel of claim 1, wherein the first charge storage node is configured to have a third potential, the second charge storage node is configured to have a fourth potential, and the third and fourth potentials are substantially the same.

7. The image sensor pixel of claim 1, wherein the first charge storage node is configured to have a third potential, the second charge storage node is configured to have a fourth potential, and the third potential is greater than the fourth potential.

8. An integrated circuit, comprising:

a first node configured to store charge;

a second node coupled to the first node and configured to receive charge from the first node; and

a transfer circuit coupling the first node to the second node, the transfer circuit comprising;

a storage region with a first variable potential configured to be controlled by a transfer signal; and

a barrier with a second variable potential greater than the first variable potential, the second variable potential also configured to be controlled by the transfer signal.

9. The integrated circuit of claim 8, wherein the storage region is laterally offset from the barrier of the transfer circuit, the storage region is proximate the second node, and the barrier is proximate the first node.

10. The integrated circuit of claim 8, wherein the transfer circuit is a modified field effect transistor.

11. The integrated circuit of claim 10, wherein a transfer gate is positioned over the barrier and the storage region.

12. The integrated circuit of claim 10, wherein a transfer gate of the field effect transistor is partitioned into two regions, one region associated with the storage region and the other region associated with the barrier.

13. The integrated circuit of claim 8, further comprising a virtual barrier coupled between the storage region and the second node, wherein the virtual barrier and the storage region together form a commonly doped region of the integrated circuit, and wherein the storage region is formed where a transfer gate is positioned over the commonly doped region and the virtual barrier is formed where a pinned layer is positioned over the commonly doped region.

14. The integrated circuit of claim 8, wherein a relative difference between the first and second variable potentials is constant across a plurality of different transfer signal voltages.

15. A method of transferring charge from a first node with a first electric potential to a second node with a second electric potential in an image sensor pixel, comprising:

increasing, responsive to a transfer signal, a third electric potential of a barrier proximate the first node such that the third electric potential is greater than the first electric potential;

increasing, responsive to the transfer signal, a fourth electric potential of a storage region coupled between the barrier and the second node such that the fourth electric potential is greater than the third electric potential; and

decreasing, responsive to the transfer signal, the fourth electric potential of the storage region such that the fourth electric potential is less than the second electric potential.

16. The method of claim 15, wherein a virtual barrier coupled between the storage region and the second node has a fifth electric potential that is less than the second electric potential, and wherein the fourth electric potential of the storage region is decreased such that it is less than the fifth electric potential.

17. The method of claim 15, wherein charge is transferred from the storage region to the second node responsive to said decreasing, further comprising:

preventing, by the virtual barrier, charge that is transferred to the second node from returning to the storage region and the first node.

18. The method of claim 15, wherein the acts of increasing the third and fourth electric potentials occur at substantially the same time responsive to the same transfer signal.

19. The method of claim 15, further comprising repeating said increasing the third and fourth potentials and decreasing the fourth potential for a plurality of pulses to transfer charge from the first node to the second node.

20. The method of claim 19, wherein charge from the first node is fully transferred to the second node only after said plurality of pulses.