SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

• US 20140252355A1
• Filed: 10/16/2012
• Published: 09/11/2014
• Est. Priority Date: 10/21/2011
• Status: Abandoned Application

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Katoh, Sumio, Nakazawa, Makoto
• Application Number:
  US14/352,931
• Publication Number:
  US 20140252355A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The semiconductor device (100A) according to the present invention has a thin film transistor (10A1) supported on a substrate; the thin film transistor (10A1) has an oxide semiconductor layer (5a1), a gate electrode (3a1), a source electrode (8a1), a drain electrode (9a1), and a metal oxide layer (6a, 7a) formed between the source electrode (8a1) and the oxide semiconductor layer (5a1) and/or between the drain electrode (9a1) and the oxide semiconductor layer (5a1); the metal oxide layer (6a, 7a) contains a metallic element included in the source electrode (8a1) and/or the drain electrode (9a1); and the thickness T1 of the oxide semiconductor layer, the thickness T2 of the metal oxide layer, and the distance D between the source electrode (8a1) and the drain electrode (9a1) satisfy the relationship D≧1.56×(T2/T1)+0.75.

Claims

1. A semiconductor device, comprising a substrate and thin film transistors supported by the substrate,

wherein the thin film transistors each include an oxide semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a metal oxide layer formed between at least either of the source electrode and the oxide semiconductor layer, or the drain electrode and the oxide semiconductor layer,

wherein the metal oxide layer includes a metal element that is included in at least one of the source electrode and the drain electrode, and

wherein a thickness T1 of the oxide semiconductor layer, a thickness T2 of the metal oxide layer, and a distance D between the source electrode and the drain electrode satisfy D≧

1.56×

(T2/T1)+0.75.

2. The semiconductor device according to claim 1, wherein the thickness T1 of the oxide semiconductor layer and the thickness T2 of the metal oxide layer further satisfy 0.21≦

(T2/T1)≦

0.57.

4. The display device according to claim 1, further comprising an etching stopper layer formed so as to cover a channel region of the oxide semiconductor layer.

5. The display device according to claim 1, wherein said metal oxide layers are formed on the oxide semiconductor layer and the source electrode and the drain electrode are formed on the metal oxide layers.

6. The semiconductor device according to claim 4, further comprising an auxiliary capacitance unit,

wherein the auxiliary capacitance unit includes:

a gate portion formed of the same conductive film as a conductive film from which the gate electrode is formed;

a gate insulating film formed on the gate portion;

another oxide semiconductor layer formed on the gate insulating film; and

another metal oxide layer formed on said another oxide semiconductor layer,

wherein the drain electrode also covers said another metal oxide layer.

7. The display device according to claim 1, wherein the metal element is titanium, aluminum, chromium, copper, tantalum, molybdenum, or tungsten.

8. The display device according to claim 1, wherein the oxide semiconductor layer and said another oxide semiconductor layer include an In—

Ga—

Zn—

O-type semiconductor.

3. A semiconductor device, comprising a substrate and thin film transistors supported by the substrate,

wherein the thin film transistors each include an oxide semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a metal oxide layer formed between at least either of the source electrode and the oxide semiconductor layer, or the drain electrode and the oxide semiconductor layer,

wherein the metal oxide layer includes a metal element that is included in at least one of the source electrode and the drain electrode, and

wherein a thickness T1 of the oxide semiconductor layer and a thickness T2 of the metal oxide layer satisfy 0.21≦

(T2/T1)≦

0.57.

17. The display device according to claim 3, further comprising an etching stopper layer formed so as to cover a channel region of the oxide semiconductor layer.

18. The display device according to claim 3, wherein said metal oxide layers are formed on the oxide semiconductor layer and the source electrode and the drain electrode are formed on the metal oxide layers.

19. The semiconductor device according to claim 17, further comprising an auxiliary capacitance unit,

wherein the auxiliary capacitance unit includes:

a gate portion formed of the same conductive film as a conductive film from which the gate electrode is formed;

a gate insulating film formed on the gate portion;

another oxide semiconductor layer formed on the gate insulating film; and

another metal oxide layer formed on said another oxide semiconductor layer

wherein the drain electrode also covers said another metal oxide layer.

20. The display device according to claim 3, wherein the metal element is titanium, aluminum, chromium, copper, tantalum, molybdenum, or tungsten.

21. The display device according to claim 3, wherein the oxide semiconductor layer and said another oxide semiconductor layer include an In—

Ga—

Zn—

O-type semiconductor.

9. A method of manufacturing a semiconductor device, comprising:

(A) forming a gate electrode on a substrate;

(B) forming a gate insulating film so as to cover the gate electrode;

(C) forming an oxide semiconductor layer on the gate insulating film;

(D) forming a source electrode and a drain electrode so as to be in contact with the oxide semiconductor layer;

(E) forming a protective film so as to cover the source electrode and the drain electrode; and

(F) forming a metal oxide layer on at least one of an area between the source electrode and the oxide semiconductor layer and an area between the drain electrode and the oxide semiconductor layer, by performing annealing,

wherein a thickness T1 of the oxide semiconductor layer, a thickness T2 of the metal oxide layer, and a distance D between the source electrode and the drain electrode satisfy D≧

1.56×

(T2/T1)+0.75.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the thickness T1 of the oxide semiconductor layer and the thickness T2 of the metal oxide layer further satisfy 0.21≦

(T2/T1)≦

0.57.

12. The method of manufacturing the semiconductor device according to claim 9, further comprising, between the step (C) and the step (D), forming an etching stopper layer covering a portion of the oxide semiconductor layer to be a channel region.

13. The method of manufacturing a semiconductor device according to claim 12,

wherein the step (A) includes forming, on the substrate, another gate portion of the same conductive film as a conductive film by which the gate electrode is formed,

wherein the step (C) includes forming another oxide semiconductor layer formed so as to overlap the gate portion across the gate insulating film,

wherein the step (D) includes forming the drain electrode so as to also be in contact with said another oxide semiconductor layer, and

wherein the step (F) includes forming another metal oxide layer between said another oxide semiconductor layer and the drain electrode.

22. The method of manufacturing the semiconductor device according to claim 10, further comprising, between the step (C) and the step (D), forming an etching stopper layer covering a portion of the oxide semiconductor layer to be a channel region.

23. The method of manufacturing a semiconductor device according to claim 22,

wherein the step (A) includes forming, on the substrate, another gate portion of the same conductive film as a conductive film by which the gate electrode is formed,

wherein the step (C) includes forming another oxide semiconductor layer formed so as to overlap the gate portion across the gate insulating film,

wherein the step (D) includes forming the drain electrode so as to also be in contact with said another oxide semiconductor layer, and

wherein the step (F) includes forming another metal oxide layer between said another oxide semiconductor layer and the drain electrode.

11. (canceled)

14-16. -16. (canceled)