MRAM HAVING SPIN HALL EFFECT WRITING AND METHOD OF MAKING THE SAME

• US 20140252439A1
• Filed: 03/06/2014
• Published: 09/11/2014
• Est. Priority Date: 03/08/2013
• Status: Abandoned Application

• Current Assignee: T3Memory USA, Inc.
• Original Assignee: T3Memory USA, Inc.
• Inventors: Guo, Yimin
• Application Number:
  US14/198,589
• Publication Number:
  US 20140252439A1
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/18 using Hall-effect devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 52/01 Manufacture or treatment
• CPC Class Codes: H10N 52/80 Constructional details

Abstract

A spin-transfer-torque magnetoresistive memory comprises apparatus and method of manufacturing a three terminal magnetoresistive memory element having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell comprises a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current.

Claims

1. A three terminal SHE spin transfer magnetoresistive memory comprising a control circuitry and at least one memory cell comprising:

a SHE metal layer provided on a surface of a substrate;

a recording layer provided on the top surface of the SHE layer having magnetic anisotropy in a film plane and having a variable magnetization direction;

a tunnel barrier layer provided on the top surface of the recording layer;

a reference layer provided on the top surface of the tunnel barrier layer having magnetic anisotropy in a film plane and having an invariable magnetization direction;

a cap layer provided on the top surface of the reference layer as an upper electric electrode;

a first bottom electrode provided on a first side of the SHE metal layer and electrically connected to the SHE metal layer;

a second bottom electrode provided on a second side of the SHE metal layer and electrically connected to the SHE metal layer;

a bit line provided on the top surface of the cap layer;

two CMOS transistors coupled the plurality of magnetoresistive memory elements through the two bottom electrodes.

There is further provided circuitry connected to the bit line, and two select transistors of each magnetoresistive memory cell.

The control circuitry coupled through the bit line and the two select transistors to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer.

2. The element of claim 1, wherein said SHE metal layer is made of a high-Z metal, preferred to be beta-phase metal of W, Ta, Hf, or doped metal of Pt, Cu, Au, Ag, Ir, Pd, doping agent is preferred to be selected from Ni, Fe, Co, Cr, Mn, V, Y and rare earth elements.

3. The element of claim 1, wherein the thickness of said SHE layer is preferred to be more than 1.5 nm and less than 10 nm.

4. The element of claim 1, wherein the resistance of said bottom electrode layer is made of highly conductive nonmagnetic metal or alloy, preferred to be Cu, Au, Ag, Ru, having a thickness preferred to be more than 2 nm and less than 20 nm.

5. The element of claim 1, wherein said bottom electrodes have width equal or less than the length of said recording layer.

6. The element of claim 1, further comprising a cap layer on said bottom electrode layer, preferred to be selected from Ta, TaN, NiCr, having a thickness in a range between 0.5 nm and 3 nm.

7. The element of claim 1, wherein said recording layer is a ferromagnetic layer, preferred to be CoFeB or CoFe, CoB.

8. The element of claim 1, wherein said recording layer is a multi-layer comprising ferromagnetic sub-layers and optional nonmagnetic insertion sub-layers containing at least one element selected from Ta, Hf, Zr, Ti, Mg, Nb, W, Mo, Ru, Al, Cu, Si and having a thickness less than 0.5 nm.

9. The element of claim 1, wherein the thickness of said recording layer is more than 1.2 nm and less than 10 nm.

10. The element of claim 1, wherein said recording layer is patterned into an in-plane shape having an aspect ratio between 1.2 and 5.

11. The element of claim 1, wherein said tunnel barrier layer is made of a metal oxide or a metal nitride, a metal oxynitride, preferred to be MgO, ZnO, MgZnO, MgN, MgON.

12. The element of claim 1, wherein said reference layer is a ferromagnetic layer having an anisotropy at least 20% larger than the anisotropy of the recording layer.

13. The element of claim 1, wherein said reference layer is a synthetic anti-ferromagnetic multilayer.

14. The element of claim 1, wherein said reference layer is a synthetic anti-ferromagnetic multilayer pinned by an anti-ferromagnetic layer.

15. A method of manufacturing a magnetoresistive memory element comprising a SHE metal layer, a recording layer, a tunnel barrier layer, a reference layer, a cap layer, two bottom electrodes and a bit line, and comprising a self-aligned patterning process to make the bottom electrodes electrically connected to a SHE metal layer and VIAs to two selected transistors.

16. The element of claim 15, wherein said SHE metal layer, said recording layer, said tunnel barrier layer, said reference layer, said cap layer are sequentially formed on the substrate.

17. The element of claim 15, further comprising a patterning process using a lithography technique and an end-point detection technique to etch down to bottom of the recording layer and form an MTJ stack having a designed width and a larger than designed length along a first direction, followed by an optional process includes O ion or N ion implantation into the etched surface.

18. The element of claim 15, further comprising a deposition of a conformal insulating film to cover entire patterned surface.

19. The element of claim 15, further comprising an ion milling process normal to the substrate surface to etch away the insulating material on top surface of the conductive layer to form a self-aligned mask comprising a remaining top hard mask and sidewall insulating film.

20. The element of claim 15, further comprising an ion milling process normal to the substrate surface having an end-point detection technique to etch down to top surface of the SHE metal layer.

21. The element of claim 15, further comprising a deposition of a nonmagnetic metal layer by an IBD process having a deposition normal to the substrate surface.

22. The element of claim 15, further comprising a rotating IBE process having a large angle to mill away the side wall metal layer.

23. The element of claim 15, further comprising a deposition of an interlayer insulating film, a chemical mechanical polishing (CMP) to flatten upper face of the interlayer insulating film.

24. The element of claim 15, further comprising a patterning process using a lithography technique and an end-point detection technique to etch down to the dielectric layer underneath said SHE metal layer and form an MTJ stack having a designed length along a first direction, followed by an optional process includes O ion or N ion implantation into the etched surface.

25. The element of claim 15, further comprising a deposition of an interlayer insulating film, a chemical mechanical polishing (CMP) to flatten upper face of the interlayer insulating film, followed by a bit line deposition and patterning