SEMICONDUCTOR DEVICE WITH INCREASED SAFE OPERATING AREA

• US 20140252472A1
• Filed: 03/11/2013
• Published: 09/11/2014
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chen, Weize, Parris, Patrice M.
• Granted Patent: US 9,537,000 B2
• Time in Patent Office: Days
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well.

Claims

1. A semiconductor device comprising:

a substrate having a surface;

a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation;

a source region disposed in the substrate adjacent the composite body region and having a second conductivity type; and

an isolation region disposed between the body contact region and the source region;

wherein;

the composite body region further comprises a body conduction path region contiguous with and under the source region; and

the body conduction path region has a higher dopant concentration level than the well.

2. The semiconductor device of claim 1, wherein:

the body conduction path region comprises a further well adjacent the body contact region; and

the further well has a higher dopant concentration level than the well in which the channel is formed.

3. The semiconductor device of claim 2, wherein the further well laterally extends across the isolation region and partially across the source region.

4. The semiconductor device of claim 1, wherein the body conduction path region extends across about an outer half of the source region, the outer half positioned distal from the channel.

5. The semiconductor device of claim 1, wherein a lateral spacing between the body conduction path region and the channel falls in a range from about 0.1 μ

m to about 0.3 μ

m.

6. The semiconductor device of claim 1, wherein:

the body conduction path region comprises a source offset region disposed adjacent and under the source region; and

the source offset region has a higher dopant concentration level than the well.

7. The semiconductor device of claim 1, wherein:

the body conduction path region comprises an opposing source extension region disposed adjacent and under the source region; and

the opposing source extension region has a higher dopant concentration level than the first well.

8. The semiconductor device of claim 1, further comprising a gate structure supported by the substrate, wherein the body conduction path region includes a region that extends under the gate structure.

9. The semiconductor device of claim 1, wherein the source region lacks an extension region having the second conductivity type.

10. The semiconductor device of claim 1, wherein the isolation region comprises a shallow trench isolation (STI) region.

11. An electronic apparatus comprising:

a substrate; and

a field-effect transistor device in the substrate, the field-effect transistor device comprising;

a first semiconductor region having a first conductivity type and comprising a well in which a channel is formed during operation; and

a second semiconductor region adjacent the first semiconductor region and having a second conductivity type;

wherein;

the first semiconductor region comprises an opposing current terminal extension region contiguous with and under the second semiconductor region and having the first conductivity type; and

the opposing current terminal extension region has a higher dopant concentration level than the well.

12. The electronic apparatus of claim 11, wherein the opposing current terminal extension region extends across a portion of the second semiconductor region distal from the channel.

13. The electronic apparatus of claim 11, wherein the second semiconductor region lacks a current terminal extension region having the second conductivity type.

14. The electronic apparatus of claim 11, further comprising an isolation region at a surface of the substrate between the second semiconductor region and a contact region of the first semiconductor region.

15. The electronic apparatus of claim 14, wherein:

the first semiconductor region further comprises a further well adjacent the contact region;

the further well has a higher dopant concentration level than the well in which the channel is formed; and

the further well laterally extends across the isolation region and partially across the second semiconductor region.

16. A method of fabricating semiconductor device, the method comprising:

forming a well of a composite body region in a substrate, the composite body region having a first conductivity type, wherein a channel is formed in the well during operation;

forming a source region in the substrate adjacent the composite body region and having a second conductivity type; and

forming a body conduction path region of the composite body region with a dopant implantation configured to form an opposing source extension region having the first conductivity type, the body conduction path region being disposed contiguous with and under the source region.

17. The method of claim 16, wherein the opposing source extension region laterally extends across a portion of the source region distal from the channel.

18. The method of claim 16, further comprising forming an isolation region at a surface of the substrate between the source region and a contact region of the composite body region.

19. The method of claim 18, further comprising forming a further well of the composite body region adjacent the contact region, the further well having a higher dopant concentration level than the well in which the channel is formed.

20. The method of claim 19, wherein the further well laterally extends across the isolation region and partially across the source region.