FinFET with Channel Backside Passivation Layer Device and Method

• US 20140252478A1
• Filed: 03/08/2013
• Published: 09/11/2014
• Est. Priority Date: 03/08/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Doornbos, Gerben, van Dal, Mark, Vellianitis, Georgios, Duriez, Blandine, Bhuwalka, Krishna Kumar, Passlack, Matthias, Oxland, Richard Kenneth, Holland, Martin Christopher, See, Yee-Chaung
• Granted Patent: US 9,412,871 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.

Claims

1. A device, comprising:

a template layer disposed on a substrate;

a buffer layer disposed over the template layer;

a channel backside passivation layer disposed over the buffer layer;

a channel layer disposed over the channel backside passivation layer; and

a gate insulator layer disposed over and in contact with the channel layer and the channel backside passivation layer, the channel backside passivation layer separating the buffer layer from the gate insulator layer.

2. The device of claim 1, wherein the buffer layer comprises aluminum.

3. The device of claim 2, wherein the channel backside passivation layer comprises one of indium phosphide and gallium antimonide.

4. The device of claim 3, wherein the channel layer comprises a III-V semiconductor compound.

5. The device of claim 1, further comprising shallow trench isolation structures (STIs) disposed on opposite sides of the channel backside passivation layer, the channel layer disposed above a top surface of the STIs, and the channel backside passivation layer having a top surface disposed above the top surface of the STIs and having a bottom surface disposed below the top surface of the STIs.

6. The device of claim 1, wherein the channel backside passivation layer comprises a shoulder region, wherein the gate insulator layer is in contact with a sidewall of the shoulder region.

7. A device, comprising:

a fin having a channel region;

a channel layer disposed in the channel region;

a buffer layer disposed under the channel layer;

a channel backside passivation layer disposed between the channel layer and the buffer layer; and

a gate insulator layer disposed over and in contact with the channel layer and the first portion of the channel backside passivation layer.

8. The device of claim 7, further comprising shallow trench isolation structures (STIs) disposed on opposite sides of the channel backside passivation layer, the channel backside passivation layer having a top surface disposed above the top surface of the STIs and having a bottom surface disposed below the top surface of the STIs.

9. The device of claim 7 wherein the channel backside passivation layer comprises a shoulder region, wherein the gate insulator layer is in contact with a sidewall of the shoulder region.

10. The device of claim 7, wherein the channel backside passivation layer has a thickness between about 4 nm and about 20 nm.

11. The device of claim 7, wherein the channel layer has a thickness between about 10 nm and about 40 nm.

12. The device of claim 7, wherein the buffer layer has a thickness between about 10 nm and about 200 nm.

13. The device of claim 7, further comprising a template layer disposed between a substrate and the buffer layer.

14. A method of forming a device, comprising:

forming a template layer over a substrate;

forming a buffer layer over the template layer;

forming a channel backside passivation layer over the buffer layer;

forming a channel layer over the channel backside passivation layer, the channel layer comprising at least a portion of a channel region; and

forming a gate insulation layer over the channel region.

15. The method of claim 14, wherein the forming the gate insulation layer comprises forming the gate insulation layer in contact with at least a portion of a sidewall of the channel backside passivation layer.

16. The method of claim 15, further comprising forming STIs in the substrate and etching back the substrate between the STIs to form a fin region, wherein the channel backside passivation layer and the channel layer are formed between the STIs and in the fin region.

17. The method of claim 16, further comprising etching back the STIs to have a height where the sidewalls of the channel layer and at least a portion of the sidewalls of the channel backside passivation layer are exposed.

18. The method of claim 15, wherein the channel layer and the channel backside passivation layer are each formed as a blanket layer, and wherein forming the channel region comprises etching away a portion of the channel layer and etching partially through a portion of the channel backside passivation layer.

19. The method of claim 15, wherein the forming the gate insulation layer comprises forming an interface control layer in contact with the channel layer.

20. The method of claim 15, wherein the channel layer comprises a III-V semiconductor, wherein the buffer layer comprises at least aluminum, and wherein the channel backside passivation layer comprises one of indium phosphide and gallium antimonide.