TRANSISTOR INCLUDING A GATE ELECTRODE EXTENDING ALL AROUND ONE OR MORE CHANNEL REGIONS

• US 20140252481A1
• Filed: 03/11/2013
• Published: 09/11/2014
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Flachowsky, Stefan, Hoentschel, Jan
• Granted Patent: US 9,006,045 B2
• Time in Patent Office: Days
• US Class Current: 257/349
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

Claims

1. A semiconductor structure, comprising:

a substrate; and

a transistor, the transistor comprising;

a raised source region and a raised drain region provided above said substrate;

one or more elongated semiconductor lines connected between said raised source region and said raised drain region, wherein a longitudinal direction of each of said one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of said substrate, each of said elongated semiconductor lines comprising a channel region;

a gate electrode that extends all around each of said channel regions of said one or more elongated semiconductor lines; and

a gate insulation layer provided between each of said one or more elongated semiconductor lines and said gate electrode.

2. The semiconductor structure of claim 1, wherein said substrate comprises a semiconductor material, said semiconductor structure further comprising a layer of an electrically insulating material provided between said substrate and at least portions of said raised source and drain regions.

3. The semiconductor structure of claim 2, wherein each of said one or more elongated semiconductor lines comprises a source region and a drain region, said channel region being provided between said source region and said drain region, at least a portion of said source region being provided below said raised source region, at least a portion of said drain region being provided below said raised drain region.

4. The semiconductor structure of claim 3, wherein a portion of said gate electrode below said one or more elongated semiconductor lines is closer to said substrate than an interface between said layer of electrically insulating material and said source and drain regions.

5. The semiconductor structure of claim 4, wherein the portion of said gate electrode below said one or more elongated semiconductor lines is provided in an opening of said layer of electrically insulating material.

6. The semiconductor structure of claim 4, wherein parts of the portion of said gate electrode below said one or more elongated semiconductor lines extend below at least one of said source and drain regions and said raised source and drain regions.

7. The semiconductor structure of claim 6, wherein an extension of the portion of said gate electrode below said one or more elongated semiconductor lines along the longitudinal direction of said one or more elongated semiconductor lines is greater than an extension of portions of said gate electrode above said elongated semiconductor lines along the longitudinal direction of said one or more elongated semiconductor lines.

8. The semiconductor structure of claim 1, further comprising a sidewall spacer formed adjacent a portion of said gate electrode located above said channel regions, said sidewall spacer separating said gate electrode from said raised source region and said raised drain region.

9. The semiconductor structure of claim 1, wherein said gate insulation layer comprises a high-k material having a greater dielectric constant than silicon dioxide and said gate electrode comprises a metal.

10. A method, comprising:

forming one or more elongated semiconductor lines on a layer of electrically insulating material, said layer of electrically insulating material being provided over a substrate comprising a different material than the layer of electrically insulating material, wherein a longitudinal direction of each of said one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of said substrate;

removing a portion of said layer of electrically insulating material below a central portion of each of said one or more elongated semiconductor lines;

forming a gate insulation layer on said central portion of each of said one or more elongated semiconductor lines; and

forming a gate electrode extending all around said central portion of each of said one or more elongated semiconductor lines, said gate insulation layer providing electrical insulation between said elongated semiconductor lines and said gate electrode.

11. The method of claim 10, wherein the removal of said portion of said layer of electrically insulating material below said central portion of each of said one or more elongated semiconductor lines forms an opening in said layer of electrically insulating material and a portion of said gate electrode below said one or more elongated semiconductor lines is formed in said opening.

12. The method of claim 10, wherein removing the portion of said layer of electrically insulating material below said central portion of each of said one or more elongated semiconductor lines comprises:

forming a first feature over a first end portion of each of said one or more elongated semiconductor lines;

forming a second feature over a second end portion of each of said one or more elongated semiconductor lines, wherein the central portion of each of said one or more elongated semiconductor lines and a portion of said layer of electrically insulating material are exposed between said first and the second feature; and

performing an etch process adapted to selectively remove a material of said layer of electrically insulating material relative to a material of said one or more elongated semiconductor lines and one or more materials exposed at surfaces of said first and the second feature.

13. The method of claim 12, wherein said etch process is substantially isotropic.

14. The method of claim 13, wherein said first feature comprises a raised source region, a first portion of a sidewall spacer formed above the first end portion of each of said one or more elongated semiconductor lines, and a first portion of a layer of dielectric material formed above said raised source region;

and

wherein the second feature comprises a raised drain region, a second portion of the sidewall spacer formed above the second end portion of each of said one or more elongated semiconductor lines, and a second portion of a layer of dielectric material formed above said raised drain region.

15. The method of claim 14, wherein the formation of said first feature and said second feature comprises:

forming a dummy gate structure over the central portion of each of said elongated semiconductor lines;

forming the sidewall spacer adjacent said dummy gate structure;

performing a selective growth process, said selective growth process forming said raised source region and said raised drain region;

depositing the layer of dielectric material over said dummy gate structure, said raised source region and said raised drain region;

planarizing the layer of dielectric material, wherein the planarization exposes said dummy gate structure; and

performing one or more etch processes to selectively remove said dummy gate structure.

16. The method of claim 15, further comprising forming a silicide in said raised source region and said raised drain region before the deposition of said layer of dielectric material.

17. The method of claim 15, further comprising in situ doping said raised source region and said raised drain region during said selective growth process.

18. The method of claim 17, further comprising performing an annealing process, wherein dopants from said raised source region diffuse into the first end portion of each of said elongated semiconductor lines and form a source region, and dopants from said raised drain region diffuse into the second end portion of each of said elongated semiconductor lines and form a drain region.

19. The method of claim 10, wherein the formation of said one or more elongated semiconductor lines comprises:

providing a semiconductor-on-insulator structure, said semiconductor-on-insulator structure comprising a layer of a semiconductor material, said substrate and said layer of electrically insulating material, said layer of electrically insulating material being provided between said substrate and said layer of semiconductor material; and

performing an etch process, said etch process removing portions of said layer of semiconductor material, wherein one or more other portions of said layer of semiconductor material are not removed in said etch process and form said one or more elongated semiconductor lines.

20. The method of claim 10, wherein said gate insulation layer comprises a high-k material having a greater dielectric constant than silicon dioxide and said gate electrode comprises a metal.