INSULATING STRUCTURE, A METHOD OF FORMING AN INSULATING STRUCTURE, AND A CHIP SCALE ISOLATOR INCLUDING SUCH AN INSULATING STRUCTURE

• US 20140252533A1
• Filed: 03/07/2013
• Published: 09/11/2014
• Est. Priority Date: 03/07/2013
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices, Inc.
• Inventors: O'Sullivan, Laurence Brendan
• Granted Patent: US 9,929,038 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A method of forming an insulating structure, comprising forming an insulating region comprising at least one electrical or electronic component or part thereof embedded within the insulating region, and forming a surface structure in a surface of the insulating region.

Claims

1. A method of forming an insulating structure, comprising

forming an insulating region comprising at least one electrical or electronic component or part thereof embedded within the insulating region, and

forming a surface structure in a surface of the insulating region.

2. A method as claimed in claim 1, in which the step of forming the insulating region comprises depositing M layers of insulator over a substrate, where M is an integer greater than or equal to one.

3. A method as claimed in claim 2, further comprising forming a component, or part of a component, over the Mth layer of insulator.

4. A method as claimed in claim 3, further comprising depositing N layers of insulator over the M layers of insulator and the or each component formed thereon.

5. A method as claimed in claim 4, further comprising selective etching of an uppermost layer of insulator so as to form a plurality of trenches thereon.

6. A method as claimed in claim 4, further comprising forming a component, or part of a component prior to depositing the M layers of insulator.

7. A method as claimed in claim 4, further comprising forming a component or part of a component or part of a component on a substrate, and depositing the M layers of insulator over a portion of the substrate containing the component or the part of the component.

8. A method as claimed in claim 7, in which the component is a transformer comprising a first coil formed beneath the M layers of insulator and a second coil formed between the Mth layer and the N layers of insulator.

9. A method as claimed in claim 1, further comprising packaging the insulating structure within an integrated circuit package, wherein the insulating structure is embedded in a packaging mould compound within the integrated circuit package.

10. A method of forming an isolator for receiving an input at a first potential, and converting it to an output as a second potential, comprising forming a input circuit on a first semiconductor substrate, forming an output circuit on a second semiconductor substrate, and interconnecting the input and output circuits by a transformer as claimed in claim 8.

11. A method of forming an isolator as claimed in claim 10, in which the transformer is formed on one of the first and second semiconductor substrates, or is formed on a third substrate.

12. A method as claimed in claim 11, in which the insulator is formed using fabrication techniques compatible with or used for the formation of integrated circuits, and the insulator is packaged within a chip scale package.

13. A method as claimed inc claim 2, in which the layers of insulator are formed by depositing and curing layers of polyimide, or other insulating polymers or oxides.

14. An insulating structure within an integrated circuit package, the insulating structure comprising an electrical or electronic component, or at least a part thereof, embedded within an insulating structure, wherein the insulating structure has a textured or ribbed surface.

15. An insulating structure as claimed in claim 14, further comprising a mould compound holding the insulating structure within the integrated circuit package, where the mould compound engages with the textured or ribbed surface of the insulating structure.

16. An insulating structure as claimed in claim 14, wherein the insulating structure is formed over a first substrate, and a first part of a signal conveying component is formed on or over the first substrate, and a second part of the signal conveying component is embedded within the insulating structure.

17. An insulating structure as claimed in claim 16, in which the signal conveying component is a transformer having first and second coils.

18. An isolator comprising a first circuit for at least receiving an input signal and a second circuit for at least outputting an output signal and a transformer formed within an insulating structure as claimed in claim 14.

19. An insulator as claimed in claim 18, in which at least the first and second circuits are formed on respective substrates, carried on respective lead frames within the integrated circuit package.

20. A method of manufacturing an electrical device comprising at least one electrical or electronic circuit provided within a package that carries connectors for establishing electrical connection the circuit, and wherein the circuit comprises at least one component encapsulated in an insulator, the method comprising forming a plurality of structures extending substantially perpendicularly to a surface of the insulator, and embedding the circuit encapsulated within the insulator in a mould compound within the package, wherein the mould compound engages with the plurality of structures at the surface of the insulator.