Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB

• US 20140252573A1
• Filed: 02/28/2014
• Published: 09/11/2014
• Est. Priority Date: 03/08/2013
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian, Bao, Xu Sheng, Chen, Kang
• Granted Patent: US 9,685,350 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 21/485 Adaptation of interconnections, e.g. engineering charges, repair techniques
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to V_SS and forms a ground plane. A second portion of the first conductive layer is electrically connected to V_DD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Claims

1. A method of making a semiconductor device, comprising:

providing a first conductive layer;

disposing a semiconductor die adjacent to the first conductive layer;

depositing an encapsulant over the first conductive layer and semiconductor die; and

forming a second conductive layer over the first conductive layer and semiconductor die.

2. The method of claim 1, wherein:

a first portion of the first conductive layer is coupled to a negative voltage terminal (V_SS); and

a second portion of the first conductive layer is coupled to a positive voltage terminal (V_DD).

3. The method of claim 1, further including:

forming an insulating layer over the first conductive layer and semiconductor die; and

forming a decoupling capacitor including the first conductive layer, insulating layer, and second conductive layer.

4. The method of claim 1, further including:

providing a carrier; and

disposing the first conductive layer and semiconductor die over the carrier.

5. The method of claim 1, further including:

providing a dummy die; and

forming the first conductive layer over the dummy die.

6. The method of claim 1, further including:

providing a substrate including a plurality of vertical interconnect structures formed through the substrate; and

forming the first conductive layer over the substrate.

7. A method of making a semiconductor device, comprising:

providing a first conductive layer;

disposing a semiconductor die adjacent to the first conductive layer; and

forming a second conductive layer over the first conductive layer and semiconductor die.

8. The method of claim 7, further including:

providing a dummy die; and

forming the first conductive layer over the dummy die.

9. The method of claim 7, wherein the first conductive layer is coupled to a negative voltage terminal (V_SS).

10. The method of claim 7, further including forming a ground plane over a surface of the semiconductor die.

11. The method of claim 7, further including disposing an interconnect structure including a third conductive layer adjacent to the semiconductor die.

12. The method of claim 7, further including:

forming an insulating layer over the first conductive layer and semiconductor die; and

forming a microstrip line over the insulating layer.

13. The method of claim 7, wherein the first conductive layer includes a patterned lead frame, patterned copper foil, resin coated tape including patterned copper, or prepeg including patterned copper.

14. A semiconductor device, comprising:

a ground plane;

a semiconductor die disposed adjacent to the ground plane; and

a conductive layer formed over the ground plane and semiconductor die.

15. The semiconductor device of claim 14, further including a substrate comprising a plurality of vertical interconnect structures formed through the substrate disposed adjacent to the semiconductor die.

16. The semiconductor device of claim 15, wherein the ground plane is formed over the substrate.

17. The semiconductor device of claim 14, further including a power plane disposed adjacent to the semiconductor die.

18. The semiconductor device of claim 14, further including a dummy die disposed adjacent to the semiconductor die, wherein the ground plane is formed over the dummy die.

19. The semiconductor device of claim 14, further including:

an insulating layer disposed between the ground plane and the conductive layer; and

a decoupling capacitor comprising the ground plane, insulating layer, and conductive layer.

20. A semiconductor device, comprising:

a first conductive layer;

a semiconductor die disposed adjacent to the first conductive layer; and

an encapsulant deposited over the first conductive layer and semiconductor die.

21. The semiconductor device of claim 20, wherein the first conductive layer is coupled to a negative voltage terminal (V_SS).

22. The semiconductor device of claim 20, further including a second conductive layer formed over the first conductive layer.

23. The semiconductor device of claim 22, further including:

an insulating layer disposed between the first conductive layer and second conductive layer; and

a decoupling capacitor including the first conductive layer, insulating layer, and second conductive layer.

24. The semiconductor device of claim 20, wherein the first conductive layer is coupled to a positive voltage terminal (V_DD).

25. The semiconductor device of claim 20, further including:

an insulating layer formed over the first conductive layer; and

a microstrip line formed over the insulating layer.