SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE VIAS

• US 20140252603A1
• Filed: 10/17/2013
• Published: 09/11/2014
• Est. Priority Date: 03/07/2013
• Status: Active Grant

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Lee, Meng-Tsung, Chiu, Shih-Kuang, Lai, Yi-Che
• Granted Patent: US 9,502,333 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/1401 Structure
• CPC Class Codes: H01L 2224/1412 Layout
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15788 Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.

Claims

1. A semiconductor device, comprising:

a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces;

an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and

a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias.

2. The semiconductor device of claim 1, further comprising a plurality of conductive bumps formed on the end portions of the conductive vias and the buffer layer on the peripheries of the end portions.

3. The semiconductor device of claim 1, further comprising at least one semiconductor element embedded in the substrate and having a gate, two gate side walls formed on two sides of the gate, respectively, and a source region and a drain region connected to the gate side walls, respectively.

4. The semiconductor device of claim 3, further comprising at least two conductors formed in the substrate and electrically connecting the source region and the drain region to the conductive vias.

5. The semiconductor device of claim 1, further comprising an under bump metallurgy formed on the end portions of the conductive vias and the buffer layer on the peripheries of the end portions.

6. The semiconductor device of claim 5, further comprising a plurality of conductive bumps formed on the under bump metallurgy.

7. The semiconductor device of claim 1, further comprising a redistribution layer formed on the insulating layer, the end portions of the conductive vias, and the buffer layer on the peripheries of the end portions.

8. The semiconductor device of claim 7, further comprising an under bump metallurgy formed on the redistribution layer.

9. The semiconductor device of claim 8, further comprising a plurality of conductive bumps formed on the under bump metallurgy.

10. The semiconductor device of claim 1, further comprising an under bump metallurgy formed on the end portions of the conductive vias and formed between the insulating layer and the buffer layer on the peripheries of the end portions, wherein the buffer layer exposes a portion of the under bump metallurgy.

11. The semiconductor device of claim 10, further comprising a plurality of conductive bumps formed on the buffer layer and the exposed portion of the under bump metallurgy.

12. The semiconductor device of claim 1, wherein the buffer layer is formed at a periphery of the insulating layer.

13. A semiconductor device, comprising:

a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces;

an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom;

a redistribution layer formed on the end portions of the conductive vias and the insulating layer;

a dielectric layer formed on the insulating layer and the redistribution layer and having a dielectric layer opening exposing a portion of the redistribution layer; and

a buffer layer formed on the dielectric layer at a periphery of the dielectric layer opening.

14. The semiconductor device of claim 13, further comprising an under bump metallurgy formed on the exposed portion of the redistribution layer and formed between the dielectric layer and the buffer layer, wherein the buffer layer exposes a portion of the under bump metallurgy.

15. The semiconductor device of claim 14, further comprising a plurality of conductive bumps formed on the buffer layer and the exposed portion of the under bump metallurgy.

16. The semiconductor device of claim 13, wherein the buffer layer is further formed at a periphery of the insulating layer.