Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package

• US 20140252641A1
• Filed: 02/21/2014
• Published: 09/11/2014
• Est. Priority Date: 03/06/2013
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Lim, See Chian, Tan, Teck Tiong, Hsiao, Yung Kuan, Fang, Ching Meng, Phua, Yoke Hor, Liao, Bartholomew
• Granted Patent: US 9,627,338 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/295 containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12 : Passive devices, e.g. 2 terminal devices
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film.

Claims

1. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor die;

disposing a first prefabricated insulating film over the semiconductor die;

disposing a conductive layer over the first prefabricated insulating film; and

forming an interconnect structure over the semiconductor die and first prefabricated insulating film.

2. The method of claim 1, further including laminating the first prefabricated insulating film over the semiconductor die.

3. The method of claim 1, wherein the first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers.

4. The method of claim 1, further including embedding the semiconductor die within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die and the interconnect structure formed over a second surface of the semiconductor die opposite the first surface.

5. The method of claim 1, further including removing a portion of the first prefabricated insulating film after disposing the first prefabricated insulating film over the semiconductor die.

6. The method of claim 1, further including disposing a second prefabricated insulating film over the first prefabricated insulating film.

7. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor die;

providing a first insulating film;

disposing the semiconductor die within the first insulating film; and

forming an interconnect structure over the semiconductor die.

8. The method of claim 7, further including disposing a second insulating film over the first insulating film.

9. The method of claim 7, wherein the first insulating film is a multilayered reinforced film.

10. The method of claim 7, further including forming a conductive layer over a surface of the first insulating film.

11. The method of claim 10, wherein the conductive layer is a thin copper foil.

12. The method of claim 7, wherein forming the interconnect structure includes:

forming a first insulating layer over the semiconductor die and first insulating film;

forming a second insulating layer over the first insulating layer;

forming a plurality of openings through the first insulating layer and second insulating layer to expose the semiconductor die; and

forming a conductive layer within the openings of the first insulating layer and second insulating layer.

13. The method of claim 7, further including disposing the semiconductor die within the first insulating film using a thermocompression process.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

providing a first insulating film; and

embedding the semiconductor die within the first insulating film.

15. The method of claim 14, wherein embedding the semiconductor die within the first insulating film further includes:

providing a vacuum hot press over the semiconductor die;

embedding the semiconductor die within the first insulating film using the vacuum hot press; and

curing the first insulating film.

16. The method of claim 14, wherein embedding the semiconductor die within the first insulating film further includes disposing a gang press over the semiconductor die to press the semiconductor die within the first insulating film.

17. The method of claim 14, further including forming an interconnect structure over the semiconductor die.

18. The method of claim 14, further including forming an under bump metallization layer over the semiconductor die.

19. The method of claim 14, further including forming a redistribution layer over the semiconductor die.

20. A semiconductor device, comprising:

a first insulating film; and

a semiconductor die embedded within the first insulating film.

21. The semiconductor device of claim 20, further including a second insulating film disposed over the first insulating film.

22. The semiconductor device of claim 20, further including a conductive layer formed over the first insulating film.

23. The semiconductor device of claim 20, further including an interconnect structure formed over the semiconductor die.

24. The semiconductor device of claim 20, wherein the first insulating film includes glass fibers, cloth, or fillers.

25. The semiconductor device of claim 20, wherein the first insulating film is prefabricated.