TEST PATTERN DESIGN FOR SEMICONDUCTOR DEVICES AND METHOD OF UTILIZING THEREOF

• US 20140253137A1
• Filed: 03/08/2013
• Published: 09/11/2014
• Est. Priority Date: 03/08/2013
• Status: Abandoned Application

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chuang, Yen, Hung, Che-Lun, Li, Hsiao-Leng
• Application Number:
  US13/790,253
• Publication Number:
  US 20140253137A1
• Time in Patent Office: Days
• US Class Current: 324/501
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 24/64 Manufacturing methods

Abstract

Methods and systems for the detection of defects in semiconductors, semiconductor devices, or substrates are provided. Semiconductors, semiconductor devices or substrates having novel test patterns and or designs are also provided. The semiconductors, semiconductor devices or substrates have a plurality of line patterns, which, in response to a responsive stimulus such as electron beam irradiation, produces a response. The responsive stimulus may include an electron beam irradiation, and the image data can be collected and processed to produce an image or images that indicate the presence or absence of surface and/or internal defects.

Claims

1. Method of inspection of a semiconductor device comprising:

providing the semiconductor device having a plurality of line patterns disposed on a substrate wherein the plurality of line patterns are connected by an interconnecting line pattern;

exposing the plurality of line patterns to a responsive stimuli; and

measuring a response of the plurality of line patterns to the responsive stimuli, wherein the response of the plurality of line patterns indicates any one of a presence and an absence of a surface defect, an internal defect, and any combination thereof.

2. The method of claim 1, wherein the plurality of line patterns are parallel to each other.

3. The method of claim 2, wherein the interconnecting line pattern is perpendicular to the plurality of line patterns.

4. The method of claim 3, wherein the interconnecting line pattern is proximate to a terminus of the plurality of line patterns.

5. The method of claim 1, wherein the responsive stimuli comprise at least one of an irradiation, a conductance, a magnetic resonance, an acoustical stimulation, and an electrical stimulation.

6. The method of claim 1, wherein the exposing the plurality of line patterns to the responsive stimuli comprises irradiating the plurality of line patterns with an electron beam radiation to provide energy to the plurality of line patterns.

7. The method of claim 6, further comprising:

collecting image data from the electron beam radiation, and

developing at least one or more images showing any one of the presence and the absence of the surface defect, the internal defect, and any combination thereof.

8. The method of claim 1, wherein the plurality of line patterns comprising a plurality of trenches on the surface of the semiconductor device and at least one conducting metal deposited in the plurality of trenches.

9. The method of claim 1, wherein the method is an in-line, continuous process.

10. The method of claim 6, wherein the electron beam radiation is supplied by an electron beam inspection tool, the electron beam inspection tool is a leap electron beam inspection tool or a continuous electron beam inspection tool.

11. The method of claim 1, additionally comprising exposing the semiconductor device to an external electrical field.

12. A semiconductor device comprising:

a substrate;

a dielectric layer disposed on the substrate;

a plurality of conductive line patterns disposed in the dielectric layer; and

at least one interconnecting line pattern configured to connect the plurality of conductive line patterns.

13. The semiconductor device of claim 12, wherein the plurality of conductive line patterns is parallel.

14. The semiconductor device of claim 13, wherein the at least one interconnecting line pattern is proximate to a terminus of and perpendicular to the plurality of conductive line patterns.

15. The semiconductor device of claim 12, wherein the dielectric layer comprises at least one of a silicon oxide and silicon nitride.

16. The semiconductor device of claim 12, wherein the plurality of conductive line patterns comprise copper.

17. A method of fabricating a semiconductor device comprising:

providing a substrate;

forming a dielectric layer on the substrate;

forming a plurality of trenches in the dielectric layer;

forming at least one interconnecting trench in the dielectric layer interconnecting the plurality of trenches; and

depositing a conductive material in the plurality of trenches and the at least one interconnecting trench.

18. The method of claim 17, wherein the plurality of trenches are disposed in parallel to each other.

19. The method of claim 17, wherein the at least one interconnecting trench is disposed perpendicular to the plurality of trenches.

20. The method of claim 19, wherein the at least one interconnecting trench is proximate to a terminus of the plurality of trenches.

21. The method of claim 17, wherein the conductive material is selected from the group consisting of aluminum, copper, tungsten, gold, any alloy thereof, and any combination thereof.

22. A system for detecting a defect in a semiconductor device comprising:

the semiconductor device having a test pattern, the semiconductor device comprising;

a substrate;

a dielectric layer disposed over the substrate;

a plurality of conductive line patterns disposed in the dielectric layer; and

at least one interconnecting line pattern configured to connect the plurality of line patterns;

an irradiating device for providing energy to the test pattern;

a receiving device to receive data resulting from the irradiating device; and

an imaging device to display an image that detects any one of a surface defect, an internal defect, and any combination thereof in the semiconductor device.

23. The system of claim 22, additionally comprising an external electric field generator located proximate to the substrate.