APPARATUS FOR DYNAMICALLY ADAPTING A CLOCK GENERATOR WITH RESPECT TO CHANGES IN POWER SUPPLY

• US 20140254734A1
• Filed: 03/07/2013
• Published: 09/11/2014
• Est. Priority Date: 03/07/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Abdelmoneum, Mohamed A., Kurd, Nasser A., Lotfy, Amr M., Abdelsalam, Mohamed A., Abd El-Mejeed, Mamdouh O.
• Granted Patent: US 10,020,931 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.

Claims

1. An integrated circuit (IC) comprising:

a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and

a phase locked loop (PLL) including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.

2. The IC of claim 1, wherein the PLL comprises a charge pump which is operable to receive the digital code word.

3. The IC of claim 2, wherein the charge pump comprises a plurality of transistors some of which are controllable by the digital code word to adjust current strength of the output of the charge pump.

4. The IC of claim 1, wherein the PLL comprises a digital filter which is operable to receive the digital code word.

5. The IC of claim 4, wherein the digital filter is characterized by coefficients some of which are adjusted by the digital code word.

6. The IC of claim 1, wherein the ring oscillator is voltage controlled oscillator (VCO).

7. The IC of claim 6, wherein the VCO comprises a plurality of delay cells each of which includes a transistor which receives the digital code word.

8. The IC of claim 1, wherein the ring oscillator is a digitally controlled oscillator (DCO).

10. The IC of claim 1, wherein the voltage droop detector comprises an Analog to Digital Converter (ADC).

9. The IC of claim 9, wherein the DCO comprises a plurality of delay cells each of which includes a transistor which receives the digital code word.

11. An apparatus comprising:

a power supply node;

a droop detector coupled to the power supply node, the droop detector to generate digital output representing voltage of the power supply node; and

a phase locked loop (PLL) coupled to the droop detector and the power supply node, the PLL to adjust its characteristics according to the digital output from the droop detector.

12. The apparatus of claim 11, wherein the PLL is at least one of:

Self-biased PLL;

Digital PLL;

or

LC PLL.

13. The apparatus of claim 11, wherein the PLL comprises a ring oscillator coupled to the power supply node, the ring oscillator to receive the digital output.

14. The apparatus of claim 11, wherein the PLL comprises a charge pump coupled to the power supply node, the charge pump to receive the digital output.

15. The apparatus of claim 11, wherein the PLL comprises a digital filter which receives the digital output.

16. A system comprising:

a memory;

a processor coupled to the memory, the processor comprising;

a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and

a phase locked loop (PLL) including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word;

a wireless interface for allowing the processor to communicate with other devices; and

a display unit.

17. The system of claim 16, wherein the processor is a multi-core processor having multiple processing cores, and wherein each processor core includes voltage droop detector.

18. The system of claim 16, wherein the PLL comprises a charge pump which is operable to receive the digital code word.

19. The system of claim 16, wherein the PLL comprises a digital filter which is operable to receive the digital code word.

20. The system of claim 16, wherein the voltage droop detector comprises an Analog to Digital Converter (ADC).