WAVEGUIDE AND SEMICONDUCTOR PACKAGING

• US 20140254979A1
• Filed: 01/08/2014
• Published: 09/11/2014
• Est. Priority Date: 03/08/2013
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Inventors: Zhang, Chunbo, Akerling, Gershon, Leong, Kevin M., Chang-Chien, Patty, Hennig, Kelly J., Ngo, Peter, Deal, William R.
• Granted Patent: US 9,478,458 B2
• Time in Patent Office: Days
• US Class Current: 385/14
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6633 Transition between different waveguide types
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2223/6683 for monolithic microwave integrated circuit [MMIC]
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81022 Cleaning the bonding area, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2224/81024 Applying flux to the bonding area
• CPC Class Codes: H01L 2224/81054 Composition of the atmosphere
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81204 with a graded temperature profile
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/055 : the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 27/14685 : Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 : Wafer level processing
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10335 : Indium phosphide [InP]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/14215 : Low-noise amplifier [LNA]
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/37001 : Yield
• CPC Class Codes: H01L 31/186 : Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
• CPC Class Codes: H01L 31/1876 : Particular processes or apparatus for batch treatment of the devices
• CPC Class Codes: H01P 11/002 : Manufacturing hollow waveguides
• CPC Class Codes: H01Q 13/02 : Waveguide horns
• CPC Class Codes: H01Q 23/00 : Antennas with active circuits or circuit elements integrated within them or attached to them

Abstract

A method and apparatus for integrating individual III-V MMICs into a micromachined waveguide package is disclosed. MMICs are screened prior to integration, allowing only known-good die to be integrated, leading to increased yield. The method and apparatus are used to implement a micro-integrated Focal Plane Array (mFPA) technology used for sub millimeter wave (SMMW) cameras, although many other applications are possible. MMICs of different technologies may be integrated into the same micromachined package thus achieving the same level of technology integration as in multi-wafer WLP integration.

Claims

1. A method of fabricating sub-millimeter wavelength (SMMW) devices, comprising the steps of:

batch processing a first wafer to include one or more DC through vias;

depositing one or more solder bumps on an upper surface of the first wafer;

batch processing a second wafer to create one or more cavities aligned with the solder bumps;

bonding a lower surface of the second wafer to the upper surface of the first wafer;

batch processing one or more third wafers of semiconductor material to form monolithic microwave integrated circuit (MMIC) chips;

dicing the one or more third wafers into individual MMIC chips; and

placing one or more MMIC chips into the cavities of the second wafer.

2. The method of claim 1 further comprising the steps of:

batch processing a fourth wafer to form one or more antennas aligned with the one or more cavities of the second wafer; and

bonding the fourth wafer to an upper surface of the second wafer.

3. The method of claim 2 wherein the one or more antennas are horn antennas.

4. The method of claim 2 wherein the first, second and fourth wafers are assembled using wafer scale assembly (WSA) techniques.

5. The method of claim 1 wherein the cavities in the second wafer comprise waveguides.

6. The method of claim 1 wherein the first wafer is GaAs, the second and fourth wafers are silicon and the third wafer is a III-V semiconductor material.

7. The method of claim 1 wherein the MMICs are tested for operability and only known-good chips are placed into the cavities of the second wafer.

8. The method of claim 1 wherein the MMICs include active circuitry.

9. The method of claim 7 wherein the MMICs are fabricated using material and processes that are not homogeneous.

10. The method of claim 1 wherein the solder bumps are aligned with the DC vias to provide an electrical interconnection to the MMIC chips.

11. A pixel for a sub-millimeter wavelength (SMMW) focal plane array (FPA) comprising:

a chip interface comprising DC through vias, and solder bumps on the upper surface of the chip interface that are aligned with the DC through vias;

a waveguide comprising one or more cavities aligned with the solder bumps on the upper surface of the chip interface;

one or more monolithic microwave integrated circuit (MMIC) chips inserted into the cavities of the waveguide; and

an antenna aligned with at least one of the cavities of the waveguide;

wherein SMMW signals are received through the antenna, transmitted through the cavities in the waveguide and processed by the MMIC chips.

12. The pixel of claim 11 wherein the chip interface is manufactured from a wafer and the waveguide and antenna are manufactured from one or more wafers.

13. The method of claim 12 wherein the chip interface wafer and the one or more waveguide and antenna wafers are integrated using a wafer scale packaging techniques.

14. The pixel of claim 11 wherein the antenna is a horn antenna.

15. The pixel of claim 11 where in the MMIC chips further comprise one or more low noise amplifiers (LNA) and one or more diodes.

16. The method of claim 11 wherein the chip interface, the waveguide, the antenna and the MMIC chips are each fabricated separately.

17. The method of claim 11 wherein the MMICs are tested for operability and only known-good chips are placed into the cavities of the waveguide.

18. A sub-millimeter wavelength (SMMW) focal plane array (FPA) comprising;

a first layer comprising a plurality of electrical connections from one side of the layer to the other;

a second layer comprising a plurality of waveguide cavities aligned with the electrical connections of the first layer;

a plurality of monolithic microwave integrated circuits (MMICs) chips inserted into the plurality of waveguide cavities and operatively connected with the electrical connections of the first layer; and

a third layer comprising a plurality of antennas, said plurality of antennas aligned with said plurality of waveguide cavities.

19. The FPA of claim 18 wherein the MMIC chips further comprise low noise amplifiers (LNA) and diodes.

20. The FPA of claim 19 wherein the first, second, third layers and the MMIC chips are each fabricated separately.

21. The FPA of claim 19 wherein the MMIC chips are fabricated from III-V semiconductor material and the first, second and third layers are batch processed.

22. The FPA of claim 18 wherein the first, second and third layers are assembled using wafer scale assembly (WSA) techniques.