Self-Aligned Passivation of Active Regions

• US 20140256105A1
• Filed: 03/11/2013
• Published: 09/11/2014
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wann, Clement Hsingjen, Yeh, Ling-Yen, Shih, Chi-Yuan, Tsai, Wei-Chun
• Granted Patent: US 9,412,847 B2
• Time in Patent Office: Days
• US Class Current: 438/283
• CPC Class Codes: H01L 21/02065 the processing being a planarization of insulating layers
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

Claims

1. A method comprising:

forming a semiconductor fin;

performing a first passivation step on a top surface of the semiconductor fin using a first passivation species;

performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species;

forming a gate stack on a middle portion of the semiconductor fin; and

forming a source or a drain region on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

2. The method for claim 1 further comprising:

recessing isolation regions on opposite sides of a semiconductor region, wherein a top portion of the semiconductor region higher than top surfaces of the isolation regions forms the semiconductor fin, wherein the first passivation step is performed before the step of recessing the isolation regions, and wherein the second passivation step is performed after the step of recessing the isolation regions.

3. The method for claim 1 further comprising:

recessing isolation regions on opposite sides of a semiconductor region, wherein a top portion of the semiconductor region higher than top surfaces of the isolation regions forms the semiconductor fin, wherein the first passivation step and the second passivation step are performed after the step of recessing the isolation regions.

4. The method for claim 3, wherein the first passivation step and the second passivation step are performed simultaneously.

5. The method of claim 1, wherein the semiconductor fin comprises germanium.

6. The method of claim 1 further comprising:

forming a dummy gate stack to cover a middle portion of the semiconductor fin;

forming an Inter-Layer Dielectric (ILD) to cover end portions of the semiconductor fin; and

removing the dummy gate stack to expose the middle portion of the semiconductor fin, wherein at least one of the first passivation step and the second passivation step is performed after the step of removing the dummy gate stack.

7. The method of claim 1 further comprising:

forming a dummy gate stack to cover a middle portion of the semiconductor fin;

forming an Inter-Layer Dielectric (ILD) to cover end portions of the semiconductor fin; and

forming contact openings in the ILD to expose the end portions of the semiconductor fin, wherein at least one of the first passivation step and the second passivation step is performed after the step of forming the contact openings.

8. A method comprising:

performing a first passivation step on a top surface of a semiconductor region using a first passivation species, wherein the semiconductor region is between isolation regions, with the top surface of the semiconductor region being substantially level with top surfaces of the isolation regions;

after the first passivation step, recessing the isolation regions, wherein a top portion of the semiconductor region higher than top surfaces of remaining portions of the isolation regions forms a semiconductor fin;

after the step of recessing, performing a second passivation step on the semiconductor fin using a second passivation species different from the first passivation species;

forming a gate stack on a middle portion of the semiconductor fin; and

forming a source or a drain region on a side of the gate stack to form a Fin Field-Effect Transistor (FinFET).

9. The method of claim 8, wherein the first passivation step is performed using the first passivation species selected from the group consisting essentially of sulfur, selenium, and combinations thereof.

10. The method of claim 8, wherein the second passivation step is performed using the second passivation species selected from the group consisting essentially of antimony, sulfur, arsenic, and combinations thereof.

11. The method of claim 10, wherein the second passivation species further comprises a second species selected from the group consisting essentially of chlorine, arsenic, and combinations thereof.

12. The method of claim 8 further comprising:

forming a dummy gate stack to cover a middle portion of the semiconductor fin;

forming an Inter-Layer Dielectric (ILD) to cover end portions of the semiconductor fin; and

removing the dummy gate stack to expose the middle portion of the semiconductor fin, wherein the second passivation step is performed after the step of removing the dummy gate stack.

13. The method of claim 8 further comprising:

forming a dummy gate stack to cover a middle portion of the semiconductor fin;

forming an Inter-Layer Dielectric (ILD) to cover end portions of the semiconductor fin; and

forming contact openings in the ILD to expose the end portions of the semiconductor fin, wherein the second passivation step is performed after the step of forming the contact openings.

14. A method comprising:

forming a semiconductor fin;

performing a first passivation step on a top surface and sidewalls of the semiconductor fin using a first passivation species, wherein the first passivation species comprises a first element and a second element, and wherein the first element is more preferred by the top surface of the semiconductor fin than by the sidewalls of the semiconductor fin, and wherein the second element is more preferred by the sidewalls of the semiconductor fin than by the top surface of the semiconductor fin;

forming a gate stack on a middle portion of the semiconductor fin; and

forming a source or a drain region on a side of the gate stack to form a Fin Field-Effect Transistor (FinFET).

15. The method of claim 14, wherein the first element is selected from the group consisting essentially of sulfur, selenium, and combinations thereof, and the second element is selected from the group consisting essentially of antimony, sulfur, arsenic, and combinations thereof.

16. The method of claim 14, wherein the first passivation species further comprises a third element, and wherein the third element is more preferred by a (111) plane of the semiconductor fin than by the top surface and the sidewalls of the semiconductor fin.

17. The method of claim 16, wherein the third element is selected from the group consisting essentially of chlorine, arsenic, and combinations thereof.

18. The method of claim 14, wherein the first passivation step comprises a method selected from the group consisting essentially of an implantation of the first passivation species, a plasma generation of the first passivation species, a gas phase of the first passivation species, and a liquid phase of the first passivation species.

19. The method of claim 18, wherein the first passivation step comprises the implantation, and wherein the method further comprises annealing the semiconductor fin after the implantation.

20. The method of claim 18 further comprising:

forming a dummy gate stack to cover a middle portion of the semiconductor fin;

forming an Inter-Layer Dielectric (ILD) to cover end portions of the semiconductor fin;

removing the dummy gate stack to expose the middle portion of the semiconductor fin; and

performing a second passivation step on the exposed middle portion of the semiconductor fin.