Semiconductor Device and Method for Forming the Same

• US 20140256113A1
• Filed: 03/15/2013
• Published: 09/11/2014
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Lien
• Granted Patent: US 9,159,604 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Abstract

A method includes forming a recess in a substrate and filling a dielectric layer in the recess. The method further includes forming a capping layer over the substrate and the dielectric layer. A top portion of the capping layer is then removed, while leaving a bottom portion of the capping layer over the dielectric layer. A gate structure is then formed over the remaining capping layer.

Claims

1. A method of forming a device, comprising:

forming a recess in a substrate comprising a semiconductor material;

filling a dielectric layer in the recess, wherein a sidewall of the dielectric layer is in contact with and forms an interface with the semiconductor material of the substrate;

forming a capping layer over the substrate and the dielectric layer, wherein the capping layer covers the interface;

removing a top portion of the capping layer, while leaving a bottom portion of the capping layer over the dielectric layer; and

forming a gate structure over the remaining capping layer.

2. The method of claim 1 wherein the dielectric layer is silicon oxide.

3. The method of claim 1 wherein the dielectric layer is deposited by subatomic chemical vapor deposition (SACVD) process, spin-on-glass process, flow-able CVD, or high density plasma (HDP).

4. The method of claim 1 wherein the capping layer is SiN, SiCN, SiON, SiC, Si-rich oxide, or combinations thereof.

5. The method of claim 1 wherein the dielectric layer has a thickness ranging from about 5 nm to about 50 nm.

6. The method of claim 1 wherein the remaining capping layer has a thickness ranging from about 3 nm to about 45 nm.

7. The method of claim 1 wherein the remaining capping layer has a thickness less than a thickness of the dielectric layer.

8. The method of claim 1 further comprising:

performing a treatment to the dielectric layer.

9. The method of claim 8 wherein the treatment is a thermal annealing process comprising a first step of H₂O steam and a second step of non-steam.

10. The method of claim 8 wherein the treatment is a thermal annealing process comprising a rapid thermal annealing (RTA) process.

11. The method of claim 1 wherein a ratio of an etching rate of the capping layer to an etching rate of the dielectric layer in a diluted HF (DHF) solution is less than about 50%.

12. The method of claim 1 wherein a ratio of an etching rate of the capping layer to an etching rate of the dielectric layer in a diluted HF (DHF) solution is less than about 1%.

13. A method of forming a device, comprising:

forming a recess in a substrate comprising a semiconductor material;

partially filling a first insulating layer in the recess, wherein a sidewall of the first insulating layer is in contact with and forms an interface with the semiconductor material of the substrate;

forming a second insulating layer over the substrate and the first insulating layer, wherein the second insulating layer covers the interface;

removing a portion of the second insulating layer over the substrate, while leaving another portion of the second insulating layer over the first insulating layer, wherein the remaining second insulating layer and the first insulating layer constitute a shallow trench isolation; and

forming a gate structure over the shallow trench isolation.

14. The method of claim 13 wherein the second insulating layer has a dielectric constant higher than a dielectric constant of the first insulating layer.

15. The method of claim 13 wherein the first insulating layer comprises an O-containing material and the second insulating layer comprises a N-containing material.

16. The method of claim 13 wherein the second insulating layer has a thickness less than a thickness of the first insulating layer.

17. The method of claim 13 wherein the step of removing the portion of the second insulating layer comprises a CMP process.

18. The method of claim 13 wherein a ratio of a thickness of the remaining second insulating layer to a thickness of the first insulating layer ranges from about 0.01 to about 0.15.

19. The method of claim 13 further comprising:

performing a thermal annealing process to the first insulating layer before forming the second insulating layer.

20. A method of forming a device, comprising:

forming a pad layer over a substrate comprising a semiconductor material;

forming a hard mask layer over the pad layer;

patterning the hard mask layer and the pad layer;

forming a recess in the substrate using the patterned hard mask layer as an etching mask;

partially filling a first dielectric layer in the recess, wherein a sidewall of the first dielectric layer is in contact with and forms an interface with the semiconductor material of the substrate;

forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer covers the interface;

removing a portion of the second dielectric layer over the patterned hard mask layer, while leaving another portion of the second dielectric layer in the recess; and

forming a gate structure over the remaining second dielectric layer.