Two-Wire Serial Interface and Protocol

• US 20140258574A1
• Filed: 03/05/2014
• Published: 09/11/2014
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Erdelyi, Janos, Bible, Steven, Li, Phil, Kovacs, Peter
• Granted Patent: US 9,910,819 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a serial transmission method using a two-wire serial interface, a master device transmits a first synchronous serial signal via the two-wire serial interface to wake-up a slave device followed by an asynchronous data transmission on one of the two-wires of the two-wire serial interface. The asynchronous data signal directly controls a function of the slave device.

Claims

1. A serial transmission method using a two-wire serial interface, comprising:

Transmitting by a master device a first synchronous serial signal via said two-wire serial interface to wake-up a slave device followed by an asynchronous data transmission on one of the two-wires of the two-wire serial interface, wherein the asynchronous data signal directly controls a function of the slave device.

2. The method according to claim 1, wherein the synchronous serial signal comprises configuration data for the slave device.

3. The method according to claim 1, wherein the synchronous serial signal comprises a calibration request.

4. The method according to claim 1, wherein the slave device is a radio frequency transmitter.

5. The method according to claim 4, wherein the transmitter is an on-off-key (OOK) radio frequency transmitter.

6. The method according to claim 5, wherein asynchronous data signal turns the transmitter on or off, respectively according to its logic state.

7. The method according to claim 1, wherein a communication via said two-wire serial interface comprises a start pattern followed by said asynchronous data transmission followed by a stop pattern.

8. The method according to claim 7, wherein the communication further comprises a wake-up wait period.

9. The method according to claim 7, wherein the communication further comprises a configuration bit within said synchronous signal.

10. The method according to claim 9, wherein when said configuration bit is set the communication comprises synchronous configuration data.

11. The method according to claim 7, wherein the communication further comprises a calibration bit within said synchronous signal.

12. The method according to claim 11, wherein when said calibration bit is set the slave device will perform a calibration.

13. A system comprising a master device and a slave device coupled through a two-wire serial interface comprising a signal line and a clock line, wherein the master device controls the slave device by transmitting a first synchronous serial signal via said two-wire serial interface to wake-up the slave device followed by an asynchronous data transmission on one of the two-wires of the two-wire serial interface, wherein the asynchronous data signal directly controls a function of the slave device.

14. The system according to claim 13, wherein the slave device is an on-off-key (OOK) radio frequency transmitter, wherein an asynchronous data signal of the asynchronous data transmission turns the transmitter on or off, respectively according to its logic state.

15. The system according to claim 13, wherein a communication via said two-wire serial interface comprises a start pattern followed by said asynchronous data transmission followed by a stop pattern.

16. The system according to claim 13, wherein the communication further comprises a wake-up wait period.

17. The system according to claim 13, wherein the communication further comprises a configuration bit within said synchronous signal.

18. The system according to claim 17, wherein when said configuration bit is set the communication comprises synchronous configuration data.

19. The system according to claim 13, wherein the communication further comprises a calibration bit within said synchronous signal.

20. The system according to claim 19, wherein when said calibration bit is set the slave device will perform a calibration.

21. An integrated circuit device comprising

a two wire serial interface,

a control unit coupled with said two-wire serial interface, and

a functional unit controlled by the control unit, wherein the control unit is operable to receive a first synchronous serial signal via said two-wire serial interface to wake-up the integrated circuit device followed by an asynchronous data transmission on one of the two-wires of the two-wire serial interface, wherein the asynchronous data signal directly controls the functional unit of the integrated circuit device.

22. The integrated circuit device according to claim 21, wherein the integrated circuit device is an on-off-key (OOK) radio frequency transmitter, wherein an asynchronous data signal of the asynchronous data transmission turns the transmitter on or off, respectively according to its logic state.

23. The integrated circuit device according to claim 21, wherein a communication received via said two-wire serial interface comprises a start pattern followed by said asynchronous data transmission followed by a stop pattern.

24. The integrated circuit device according to claim 21, wherein the communication further comprises a wake-up wait period during which the operational units of integrated circuit device are woken up from a sleep mode by said control unit.

25. The integrated circuit device according to claim 21, wherein the communication further comprises a configuration bit within said synchronous signal.

26. The integrated circuit device according to claim 25, wherein when said configuration bit is set the communication comprises synchronous configuration data.

27. The integrated circuit device according to claim 21, wherein the communication further comprises a calibration bit within said synchronous signal.

28. The integrated circuit device according to claim 27, wherein when said calibration bit is set the integrated circuit device will perform a calibration.

29. The integrated circuit device according to claim 21, wherein the IC device is arranged within a 6-pin housing.