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CPU Current Ripple and OCV Effect Mitigation

  • US 20140258765A1
  • Filed: 03/05/2013
  • Published: 09/11/2014
  • Est. Priority Date: 03/05/2013
  • Status: Active Grant
First Claim
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1. A method of reducing transient variations in power supplied to a processor comprising a plurality of functional processing units, comprising:

  • generating at least first and second clock signals, the second clock signal having a phase offset relative to the first clock signal;

    clocking a first functional unit of the processor with the first clock signal;

    clocking a second functional unit of the processor with the second clock signal; and

    synchronizing data transfer between the second functional unit and a circuit clocked by the first clock signal by interposing a clock phase synchronization circuit on a data path between the second functional unit and the circuit clocked by the first clock signal.

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