METHOD AND SYSTEMS FOR DETECTING AND ISOLATING HARDWARE TIMING CHANNELS
First Claim
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1. A method for detecting a timing channel in a hardware design, the method comprising:
- receiving a hardware design;
synthesizing at least one portion of the hardware design with gate level primitives;
adding tracking logic to the gate level primitives to monitor information flow through the gate level primitives;
simulating sets of inputs to the gate level primitives including added taint inputs to identify information flows by generating outputs from the gate level primitives for every clock tick while changing only taint inputs;
separating timing flows from informational flows by conducting input to output deterministic traces to isolate functional flows in the information flows.
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Abstract
A method for detecting a timing channel in a hardware design includes synthesizing the hardware design to gate level. Gate level information flow tracing is applied to the gate level of the hardware design via a simulation to search for tainted flows. If a tainted flow is found, a limited number of traces are selected. An input on the limited number of traces is simulated to determine whether the traces are value preserving with respect to taint inputs, and to determine that a timing flow exists if the traces are value preserving with respect to the taint inputs.
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Citations
9 Claims
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1. A method for detecting a timing channel in a hardware design, the method comprising:
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receiving a hardware design; synthesizing at least one portion of the hardware design with gate level primitives; adding tracking logic to the gate level primitives to monitor information flow through the gate level primitives; simulating sets of inputs to the gate level primitives including added taint inputs to identify information flows by generating outputs from the gate level primitives for every clock tick while changing only taint inputs; separating timing flows from informational flows by conducting input to output deterministic traces to isolate functional flows in the information flows. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for detecting a timing channel in a hardware design, the method comprising:
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synthesizing the hardware design to gate level; applying gate level information flow tracing to the gate level of the hardware design via a simulation to search for tainted flows; if a tainted flow is found, selecting a limited number of traces, simulating an input on the limited number of traces, determining whether the traces are value preserving with respect to taint inputs, and determining that a timing flow exists if the traces are value preserving with respect to the taint inputs.
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Specification