DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD

• US 20140264433A1
• Filed: 03/14/2013
• Published: 09/18/2014
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hu, Jun, Bobde, Madhur, Yilmaz, Hamza
• Granted Patent: US 9,048,282 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

Claims

1. An insulated gate bipolar transistor (IGBT) device supported in a semiconductor substrate wherein:

the semiconductor substrate comprising an epitaxial layer of a first conductivity type supported on a bottom layer of a second conductivity type electrically contacting a collector electrode disposed on a bottom surface of the semiconductor substrate;

the IGBT device further comprises a body region of the second conductivity type disposed near a top surface of the semiconductor substrate encompassing a source region of the first conductivity type below a top surface of the semiconductor substrate;

the epitaxial layer further includes an upper heavily doped layer having a higher dopant concentration of the first conductivity type below the body region; and

the IGBT device further comprises a first trench gate and a second trench gate disposed on two opposite sides of the body region and a planar gate disposed on the top surface of the semiconductor substrate extending laterally over the first trench gate to the body region.

2. The IGBT device of claim 1 further comprising:

a vertical gate oxide covering and encapsulating the planar gate.

3. The IGBT device of claim 1 wherein:

the first trench gate is electrically connected to a gate electrode.

4. The IGBT device of claim 1 wherein:

the planar gate is electrically connected to a gate electrode.

5. The IGBT device of claim 1 wherein:

the second trench gate is electrically connected to a source electrode.

6. The IGBT device of claim 1 wherein:

the second trench gate is electrically connected to a gate electrode.

7. The IGBT device of claim 1 further comprising:

a vertical gate oxide having a thickness of approximately 1000 Angstroms covering and encapsulating the planar gate.

8. The IGBT device of claim 1 wherein:

the first trench gate and the second trench gate are padded with a gate insulation layer and filled with a polysilicon layer.

9. The IGBT device of claim 1 wherein:

the first trench gate and the second trench gate are padded with a gate insulation layer having a thickness of approximately 5000 Angstroms and the first and second trench gates are filled with a polysilicon layer.

10. The IGBT device of claim 1 wherein:

the first trench gate and the second trench gate extend vertically to approximately a bottom surface of the upper heavily dope region above the epitaxial layer.

11. The IGBT device of claim 1 wherein:

the upper heavily doped region comprising a heavily N-doped region above the epitaxial layer of an N-type conductivity disposed above the substrate of a P-type conductivity type.

12. The IGBT device of claim 1 further comprising:

a floating buried ring disposed below a trench bottom surface of the second trench gate.

13. The IGBT device of claim 1 further comprising:

a floating buried ring of the second conductivity type disposed below a trench bottom surface of a second trench.

14. The IGBT device of claim 1 wherein:

the upper heavily doped layer functioning together with the epitaxial layer as a base region of the IGBT, and the body region functioning as a channel region from the source region to the base region of the IGBT.

15. The IGBT device of claim 1 wherein:

the planar gate extends substantially perpendicularly to the first and second trench gates.

16. The IGBT device of claim 1 further comprising:

a floating buried ring type disposed below a trench bottom surface of a second trench;

the planar gate extends substantially perpendicularly to the first and second trench gates; and

the floating buried ring extending laterally as a stripe aligned with the first and second trench gates.

17. The IGBT device of claim 1 further comprising:

a floating buried ring type disposed below a trench bottom surface of a second trench;

the planar gate extends substantially perpendicularly to the first and second trench gates; and

the floating buried ring comprising buried ring as islands disposed at selected locations along a second trench extending perpendicular to the planar gate.

18. A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising:

preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type;

applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate;

implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and

forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

19. The method of claim 18 further comprising:

forming a vertical gate oxide covering and encapsulating the planar gate.

20. The method of claim 18 further comprising:

electrically connecting the first trench gate to a gate electrode.

21. The method of claim 18 further comprising:

electrically connecting the planar gate to a gate electrode.

22. The method of claim 18 further comprising:

electrically connecting the second trench gate to a source electrode.

23. The method of claim 18 further comprising:

electrically connecting the second trench gate to a gate electrode.

24. The method of claim 18 further comprising:

forming a vertical gate oxide having a thickness of approximately 1000 Angstroms covering and encapsulating the planar gate.

25. The method of claim 18 further comprising:

padding the first trench gate and the second trench gate with a gate insulation layer before filling the trenches with the polysilicon layer.

26. The method of claim 18 further comprising:

implanting through the second trench to form a floating buried ring below a trench bottom surface of the second trench gate.

27. The method of claim 18 further comprising:

implanting dopants of the second conductivity type through the second trench to form a floating buried ring below a trench bottom surface of the second trench gate.