METHOD OF FORMING A HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE

• US 20140264456A1
• Filed: 03/13/2014
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Salih, Ali, Parsey, John Michael Jr.
• Application Number:
  US14/208,803
• Publication Number:
  US 20140264456A1
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 21/02365 Forming inorganic semiconducting materials on a substrate for light-sensitive devices H01L31/00
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7789 the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body

Abstract

In an embodiment, a semiconductor device is formed by a method that includes, providing a base substrate of a first semiconductor material, and forming a layer that is one of SiC or a III-V series material on the base substrate. In a different embodiment, the base substrate may be one of silicon, porous silicon, or porous silicon with nucleation sites formed thereon, or silicon in a (111) plane.

Claims

1. A method of forming a HEM device comprising:

providing a base substrate of a first semiconductor material that includes silicon;

forming a layer that is one of GaN or SiC or other III-N or III-V or II-VI series material overlying the base substrate;

forming a friable region near an interface of the layer and an underlying material;

separating a portion of the layer from the base substrate;

attaching the portion of the layer to an intermediate substrate; and

forming the HEM device in the portion of the layer.

2. The method of claim 1 wherein separating the portion of the layer includes separating the layer into two sections along a long axis of the layer that is substantially parallel to the surface of the base substrate.

3. The method of claim 1 further including attaching the intermediate substrate to the portion of the layer prior to separating the portion of the layer.

4. A method of forming a semiconductor device comprising:

providing a base substrate of a first semiconductor material that includes silicon; and

forming a layer that is one of GaN or SiC or other III-N or III-V or II-VI series material on the base substrate.

5. The method of claim 4 wherein providing the base substrate includes providing a porous silicon base substrate.

6. The method of claim 5 further including forming a friable region in the layer.

7. The method of claim 6 further including bonding an intermediate substrate to the layer.

8. The method of claim 7 further including separating the intermediate substrate and at least a portion of the layer from the base substrate.

9. The method of claim 6 further including separating at least a portion of the layer from the base substrate.

10. The method of claim 9 further including bonding the portion of the layer to an intermediate substrate.

11. The method of claim 10 further including cleaning the base substrate and forming another layer on the base substrate wherein the another layer is one of GaN or SiC or other III-N or III-V or II-VI series material.

12. The method of claim 4 further including forming the HEM device that includes the layer.

13. The method of claim 4 wherein providing the base substrate includes providing a porous silicon base substrate having pores on a surface of the base substrate;

forming an insulator on and within the pores; and

planarizing the surface to form silicon nucleation sites on the surface of the base substrate.

14. The method of claim 4 wherein forming the layer includes forming a layer that includes a plurality of III series layers.

15. The method of claim 4 wherein forming the layer includes forming an AlN layer and forming a GaN layer on the AlN layer.

16. The method of claim 4 wherein providing the base substrate includes providing a silicon base substrate having a surface in a (111) plane;

and

forming a layer of GaN on the surface of the silicon base substrate wherein the GaN is formed with a (0001) plane on (111) plane of the silicon base substrate.

17. A HEM device comprising:

a silicon base substrate having a surface in a (111) plane; and

a layer of GaN or other II-V or II-VI material on the surface of the silicon base substrate wherein the layer is formed with a (0001) plane on the (111) plane of the silicon base substrate.

18. The HEM device of claim 17 further including a channel material on at least a portion of the layer.

19. The HEM device of claim 18 wherein the channel material includes AlGaN.

20. The HEM device of claim 18 further including a gate material overlying the channel material.