METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE

• US 20140264479A1
• Filed: 03/12/2013
• Published: 09/18/2014
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Cai, Xiuyu, Xie, Ruilong, Khakifirooz, Ali, Cheng, Kangguo
• Granted Patent: US 8,841,711 B1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least portions of the second liner layer relative to the first liner layer, forming a second layer of insulating material above the first layer of insulating material, performing at least one second etching process to remove at least portions of the first and second layers of insulating material and at least portions of the first liner layer so as to thereby expose an outer surface of the sidewall spacer, and forming a conductive contact that contacts the exposed outer surface of the sidewall spacer and a source/drain region of the transistor.

Claims

1. A method of forming a transistor, comprising:

forming a gate structure above a semiconductor substrate;

forming a sidewall spacer adjacent said gate structure;

forming a first liner layer on at least said sidewall spacer;

forming a second liner layer on said first liner layer;

forming a first layer of insulating material above said substrate and adjacent said second liner layer;

performing at least one etching process to selectively remove at least portions of said second liner layer relative to said first liner layer and said first layer of insulating material so as to thereby form a space between said first layer of insulating material and said first liner layer; and

forming a second layer of insulating material above said first layer of insulating material.

2. The method of claim 1, wherein said sidewall spacer and said second liner layer are comprised of silicon nitride and said first liner layer and said first layer of insulating material are comprised of silicon dioxide.

3. The method of claim 2, wherein said second layer of insulating material is comprised of silicon dioxide.

4. The method of claim 1, wherein said gate structure comprises a sacrificial gate electrode.

5. The method of claim 1, wherein, after forming said second layer of insulating material, said space between said first layer of insulating material and said first liner layer remains substantially unfilled.

6. The method of claim 1, further comprising:

performing at least one etching process to remove at least portions of said first and second layers of insulating material and at least portions of said first liner layer so as to thereby expose an outer surface of said sidewall spacer; and

forming a conductive contact that is in physical contact with said exposed outer surface of said sidewall spacer and conductively coupled to a source/drain region of said transistor.

7. The method of claim 1, wherein said first and second layers of insulating material are comprised of silicon dioxide or a material having a dielectric constant less than 3.

8. A method of forming a transistor, comprising:

forming a gate structure above a semiconductor substrate;

forming a sidewall spacer adjacent said gate structure;

forming a first liner layer on at least said sidewall spacer;

forming a second liner layer on said first liner layer;

forming a first layer of insulating material above said substrate and adjacent said second liner layer;

performing at least one first etching process to selectively remove at least portions of said second liner layer relative to said first liner layer;

forming a second layer of insulating material above said first layer of insulating material;

performing at least one second etching process to remove at least portions of said first and second layers of insulating material and at least portions of said first liner layer so as to thereby expose an outer surface of said sidewall spacer; and

forming a conductive contact that is in physical contact with said exposed outer surface of said sidewall spacer and conductively coupled to a source/drain region of said transistor.

9. The method of claim 8, wherein said sidewall spacer and said second liner layer are comprised of silicon nitride and said first liner layer and said first layer of insulating material are comprised of silicon dioxide.

10. The method of claim 9, wherein said second layer of insulating material is comprised of silicon dioxide.

11. The method of claim 8, wherein said gate structure comprises a sacrificial gate electrode.

12. The method of claim 8, wherein said first and second layers of insulating material are comprised of silicon dioxide or a material having a dielectric constant less than 3.

13. A transistor device, comprising:

a gate structure positioned above a semiconductor substrate;

a sidewall spacer positioned adjacent opposite sides of said gate structure;

a first layer of insulating material positioned above said substrate, said first layer of insulating material being laterally spaced apart from and not in contact with said sidewall spacer;

a second layer of insulating material positioned above said first layer of insulating material, said second layer of insulating material contacting said sidewall spacer; and

first and second air gaps positioned on opposite sides of said gate structure, wherein each of said first and second air gaps is defined, in part, by an outer surface of said sidewall spacer, said first layer of insulating material and said second layer of insulating material.

14. The device of claim 13, wherein each of said first and second air gaps is further defined by an upper surface of said substrate.

15. The device of claim 13, wherein each of said first and second air gaps is further defined by at least one additional layer of insulating material positioned between said first layer of insulating material and said substrate, said at least one additional layer of insulating material being laterally spaced apart from and not in contact with said sidewall spacer.

16. The device of claim 13, wherein said device further comprises first and second conductive contacts that are positioned on opposite sides of said gate structure, each of said first and second conductive contacts being conductively coupled to a source/drain region of said transistor, wherein said first air gap is positioned between said first conductive contact and said gate structure and said second air gap is positioned between said second conductive structure and said gate structure.

17. A transistor device, comprising:

a gate structure positioned above a semiconductor substrate;

a sidewall spacer positioned adjacent opposite sides of said gate structure;

a first layer of insulating material positioned above said substrate, said first layer of insulating material being laterally spaced apart from and not in contact with said sidewall spacer;

a second layer of insulating material positioned above said first layer of insulating material, said second layer of insulating material contacting said sidewall spacer; and

first and second air gaps positioned on opposite sides of said gate structure, wherein each of said first and second air gaps is defined, in part, by an outer surface of said sidewall spacer, said first layer of insulating material, said second layer of insulating material and an upper surface of said substrate.

18. The device of claim 17, wherein each of said first and second air gaps is further defined by at least one additional layer of insulating material positioned between said first layer of insulating material and said substrate, said at least one additional layer of insulating material being laterally spaced apart from and not in contact with said sidewall spacer.

19. The device of claim 17, wherein said device further comprises first and second conductive contacts that are positioned on opposite sides of said gate structure, each of said first and second conductive contacts being conductively coupled to a source/drain region of said transistor, wherein said first air gap is positioned between said first conductive contact and said gate structure and said second air gap is positioned between said second conductive structure and said gate structure.

20. A transistor device, comprising:

a gate structure positioned above a semiconductor substrate;

a source/drain region;

a sidewall spacer positioned adjacent opposite sides of said gate structure; and

a conductive contact that is in physical contact with an outer surface of said sidewall spacer and conductively coupled to said source/drain region of said transistor.