DIRECT-DRAIN TRENCH FET WITH SOURCE AND DRAIN ISOLATION

• US 20140264567A1
• Filed: 02/05/2014
• Published: 09/18/2014
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: CHALLA, Ashok
• Granted Patent: US 9,018,700 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a general aspect, an apparatus can include a semiconductor layer of a first conductivity type, the semiconductor layer having a top-side surface. The apparatus can also include a well region of a second conductivity type opposite the first conductivity type, the well region being disposed in an upper portion of the semiconductor layer. The apparatus can further include a gate trench disposed in the semiconductor layer, the gate trench extending through the well region, and a drain contact disposed, at least in part, on the top-side surface of the semiconductor layer, the drain contact being adjacent to the well region. The apparatus can still further include an isolation trench disposed between the drain contact and the gate trench in the semiconductor layer, the isolation trench extending through the well region.

Claims

1. An apparatus comprising:

a semiconductor layer of a first conductivity type, the semiconductor layer having a top-side surface;

a well region of a second conductivity type opposite the first conductivity type, the well region being disposed in an upper portion of the semiconductor layer;

a gate trench disposed in the semiconductor layer, the gate trench extending through the well region;

a drain contact disposed, at least in part, on the top-side surface of the semiconductor layer, the drain contact being adjacent to the well region; and

an isolation trench disposed between the drain contact and the gate trench in the semiconductor layer, the isolation trench extending through the well region.

2. The apparatus of claim 1, further comprising:

a dielectric; and

an isolation electrode disposed within the dielectric in the isolation trench, the isolation electrode being configured to operate at a floating potential.

3. The apparatus of claim 1, further comprising a dielectric disposed within the isolation trench, the dielectric substantially filling the isolation trench.

4. The apparatus of claim 1, wherein the isolation trench is a first isolation trench, the apparatus further comprising a second isolation trench, the second isolation trench being disposed between the first isolation trench and the drain contact.

5. The apparatus of claim 1, wherein the isolation trench is a first isolation trench, the apparatus further comprising a second isolation trench, the second isolation trench being disposed between the first isolation trench and the gate trench.

6. The apparatus of claim 1, further comprising:

a gate dielectric disposed on a sidewall of the gate trench;

a gate electrode disposed in the gate trench and disposed within the gate dielectric; and

a source region disposed in the well region, the source region being adjacent to the gate trench.

7. The apparatus of claim 1, further comprising a drain contact trench disposed in the semiconductor layer, at least a portion of the drain contact being disposed within the drain contact trench.

8. The apparatus of claim 1, further comprising a drain implant region of the first conductivity type, the drain contact being disposed on the drain implant region.

9. The apparatus of claim 1, wherein the gate trench is a first gate trench, the apparatus further comprising:

a termination trench disposed in the semiconductor layer and disposed between the gate trench and the isolation trench, the termination trench extending through the well region;

at least one termination electrode disposed in the termination trench;

an isolation electrode disposed in the isolation trench;

a dielectric disposed in the termination trench, disposed in the isolation trench and disposed on the well region between the termination trench and the isolation trench, the dielectric insulating the termination electrode from, at least, the semiconductor layer and insulating the isolation electrode from the semiconductor layer and the well region; and

a second gate trench disposed between the first gate trench and the second gate trench, the second gate trench extending through the well region.

10. The apparatus of claim 1, wherein the well region is a first well region, the gate trench is a first gate trench and the isolation trench is a first isolation trench, the apparatus further comprising:

a second well region disposed in the semiconductor layer on an opposite side of the drain contact as the first well region;

a second gate trench disposed in the semiconductor layer on the opposite side of the drain contact, the second gate trench extending thorough the second well region; and

a second isolation trench disposed between the drain contact and the second gate trench in the semiconductor layer, the second isolation trench extending through the second well region.

11. The apparatus of claim 1, wherein the drain contact is a first drain contact and the isolation trench is a first isolation trench, the apparatus further comprising:

a second drain contact disposed, at least in part, on the top-side surface of the semiconductor layer and on an opposite side of the gate trench as the first drain contact; and

a second isolation trench disposed between the second drain contact and the gate trench in the semiconductor layer, the second isolation trench extending through the well region.

12. A direct-drain trench field effect transistor (FET) comprising:

a semiconductor layer of a first conductivity type;

an active region disposed in the semiconductor layer;

an isolation region disposed in the semiconductor layer;

a drain region disposed in the semiconductor layer, the isolation region being disposed between the active region and the drain region; and

a well region of a second conductivity type opposite the first conductivity type, the well region being disposed in the semiconductor layer and extending from the active region through the isolation region to the well region,

the drain region including a direct-drain portion disposed, at least in part, on the semiconductor layer,

the isolation region including an isolation trench disposed in the semiconductor layer and extending through the well region.

13. The direct-drain trench FET of claim 12, wherein the active region includes:

a gate trench extending through the well region;

a shield dielectric disposed on a gate trench sidewall in a lower portion of the gate trench;

a shield electrode disposed within the shield dielectric;

an inter-electrode dielectric disposed on the shield electrode;

a gate dielectric disposed on the gate trench sidewall in an upper portion of the gate trench;

a gate electrode disposed within the gate dielectric; and

a source region of the first conductivity type, the source region being disposed in the well region and adjacent to the gate trench.

14. The direct-drain trench FET of claim 13, wherein the active region further includes a source interconnect layer, the source interconnect layer including a metal-filled contact disposed in the well region and in contact with the source region.

15. The direct-drain trench FET of claim 13, wherein the active region further includes:

a termination trench extending through the well region, the termination trench being disposed between the gate trench and the isolation trench.

16. The direct-drain trench FET of claim 12, further comprising:

an isolation electrode disposed in the isolation trench; and

an isolation dielectric disposed in the isolation trench, the isolation dielectric insulating the isolation electrode from the well region and the semiconductor layer.

17. The direct-drain trench FET of claim 12, further comprising an isolation dielectric disposed in the isolation trench, the isolation dielectric substantially filling the isolation trench.

18. A method comprising:

forming a semiconductor layer of a first conductivity type, the semiconductor layer having a top-side surface;

forming a well region of a second conductivity type, the well region being disposed in an upper portion of the semiconductor layer;

forming a gate trench disposed in the semiconductor layer, the gate trench extending through the well region;

forming a drain contact on, at least in part, the top-side surface of the semiconductor layer, the drain contact being adjacent to the well region; and

forming an isolation trench in the semiconductor layer between the drain contact and the gate trench, the isolation trench extending through the well region.

19. The method of claim 18, further comprising forming a dielectric in the isolation trench, the dielectric substantially filling the trench.

20. The method of claim 18, further comprising:

forming a dielectric on a sidewall of the isolation trench;

forming an isolation electrode within the dielectric, the dielectric insulating the isolation electrode from the semiconductor layer and the well region.