Merged Active Devices on a Common Substrate
First Claim
Patent Images
1. An arrangement, comprising:
- a plurality of gates corresponding to stacked devices, wherein the stacked devices are stacked across an active area common to the plurality of gates;
a plurality of conducting channels formed, during operation of the arrangement, underneath each gate from among the plurality of gates;
a first source contact in correspondence of a first gate from among the plurality of gates;
a last drain contact in correspondence of a last gate from among the plurality of gates;
a first drain side of the active area in correspondence of the first gate;
a last source side of the active area in correspondence of the last gate; and
one or more drain sides and one or more source sides of the active area, wherein each drain side and each source side is in correspondence of each gate other than the first gate and the last gate, and wherein contiguous regions of the active area comprise drain sides and source sides in correspondence of adjacent gates,wherein, during operation of the arrangement, current is adapted to travel through the contiguous regions of the active area comprised of drain sides and source sides in correspondence of adjacent gates as well as through the conducting channels formed underneath each of corresponding gates overlapping the active area, andwherein at least one of the stacked devices is different from the other stacked devices.
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Abstract
Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented.
8 Citations
21 Claims
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1. An arrangement, comprising:
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a plurality of gates corresponding to stacked devices, wherein the stacked devices are stacked across an active area common to the plurality of gates; a plurality of conducting channels formed, during operation of the arrangement, underneath each gate from among the plurality of gates; a first source contact in correspondence of a first gate from among the plurality of gates; a last drain contact in correspondence of a last gate from among the plurality of gates; a first drain side of the active area in correspondence of the first gate; a last source side of the active area in correspondence of the last gate; and one or more drain sides and one or more source sides of the active area, wherein each drain side and each source side is in correspondence of each gate other than the first gate and the last gate, and wherein contiguous regions of the active area comprise drain sides and source sides in correspondence of adjacent gates, wherein, during operation of the arrangement, current is adapted to travel through the contiguous regions of the active area comprised of drain sides and source sides in correspondence of adjacent gates as well as through the conducting channels formed underneath each of corresponding gates overlapping the active area, and wherein at least one of the stacked devices is different from the other stacked devices. - View Dependent Claims (3)
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2. An arrangement, comprising:
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a plurality of gates corresponding to stacked devices, wherein the stacked devices are stacked across an active area common to the plurality of gates; a first source contact in correspondence of a first gate from among the plurality of gates; a last drain contact in correspondence of a last gate from among the plurality of gates; a first drain side of the active area in correspondence of the first gate; a last source side of the active in correspondence of the last gate; and one or more drain sides and one or more source sides of the active area, wherein each drain side and each source side is in correspondence of each gate other than the first gate and the last gate, and wherein contiguous regions of the active area comprise drain sides and source sides in correspondence of adjacent gates, wherein at least one of the stacked devices is different from the other stacked devices. - View Dependent Claims (4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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5. An arrangement, comprising:
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a plurality of N gates corresponding to stacked devices, wherein the stacked devices are stacked across an active area common to the plurality of N gates, wherein N represents an integer, at least one of the stacked devices being different from the other stacked devices; a first source contact in correspondence of a first gate G1 from among the plurality of N gates; and a last drain contact in correspondence of a last gate GN from among the plurality of N gates, wherein, during operation of the arrangement, current travels between each of the plurality of gates through regions that are located between gates G1 and G2, . . . , and between gates GN-1 and GN, of the active area common to the plurality of N gates.
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17. A method, comprising:
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providing a plurality of gates corresponding to stacked devices, wherein the stacked devices are stacked across an active area common to the plurality of gates, at least one of the stacked devices being different from the other stacked devices; providing a plurality of conducting channels formed underneath each gate from among the plurality of gates; providing a first source contact in correspondence of a first gate from among the plurality of gates; providing a last drain contact in correspondence of a last gate from among the plurality of gates; providing a first drain side of the active area in correspondence of the first gate; providing a last source side of the active area in correspondence of the last gate; providing one or more drain sides and one or more source sides of the active area, wherein each drain side and each source side is in correspondence of each gate other than the first gate and the last gate, and wherein contiguous regions of the active area comprise drain sides and source sides in correspondence of adjacent gates; and applying an input signal to the first gate and a DC bias between the last drain contact and the first source contact in a manner such that current travels through the contiguous regions of the active area comprised of drain sides and source sides in correspondence of adjacent gates as well as through the conducting channels formed underneath each of corresponding gates overlapping the active area. - View Dependent Claims (20, 21)
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18. A method, comprising:
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providing a plurality of gates corresponding to stacked devices, wherein the stacked devices are stacked across an active area common to the plurality of gates, at least one of the stacked devices being different from the other stacked devices; providing a first source contact in correspondence of a first gate from among the plurality of gates; providing a last drain contact in correspondence of a last gate from among the plurality of gates; providing a first drain side of the active area in correspondence of the first gate; providing a last source side of the active in correspondence of the last gate; and providing one or more drain sides and one or more source sides of the active area, wherein each drain side and each source side is in correspondence of each gate other than the first gate and the last gate, and wherein contiguous regions of the active area comprise drain sides and source sides in correspondence of adjacent gates.
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19. A method, comprising:
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providing a plurality of N gates corresponding to stacked devices which are stacked across an active area common to the plurality of N gates, wherein N represents an integer, at least one of the stacked devices being different from the other stacked devices; providing a first source contact in correspondence of a first gate G1 from among the plurality of N gates; providing a last drain contact in correspondence of a last gate GN from among the plurality of N gates; and applying an input signal to the first gate G1 and a DC bias between a last drain contact in correspondence of the last gate GN and a first source contact in correspondence of the first gate G1 in a manner such that current travels between each of the plurality of gates through regions, which are located between gates G1 and G2, . . . , and between gates GN-1 and GN, of the active area common to the plurality of N gates.
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Specification