ENGINEERED SUBSTRATES FOR SEMICONDUCTOR EPITAXY AND METHODS OF FABRICATING THE SAME

• US 20140264763A1
• Filed: 03/14/2014
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: X-Celeprint Limited
• Original Assignee: Semprius, Inc.
• Inventors: Meitl, Matthew, Burroughs, Scott
• Granted Patent: US 9,362,113 B2
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02645 Seed materials
• CPC Class Codes: H01L 21/02647 Lateral overgrowth

Abstract

In a method for fabricating an engineered substrate for semiconductor epitaxy, an array of seed structures is assembled on a surface of the substrate. The seed structures in the array have substantially similar directional orientations of their crystal lattices, and are spatially separated from each other. Semiconductor materials are selectively epitaxially grown on the seed structures, such that a rate of growth of the semiconductor materials on the seed structures is substantially higher than a rate of growth of the semiconductor materials on regions of the surface. The semiconductor materials assume a lattice constant and directional orientation of crystal lattice that are substantially similar or identical to those of the seed structures. Related devices and methods are also discussed.

Claims

1. (canceled)

2. A method of fabricating a semiconductor device, the method comprising:

assembling an array of discrete seed structures on a surface of a target substrate different than a source substrate thereof such that respective crystal lattices of the discrete seed structures of the array have substantially similar orientations; and

selectively growing respective semiconductor layers on the discrete seed structures.

3. The method of claim 2, wherein neighboring ones of the discrete seed structures on the surface of the target substrate are separated by about 10 micrometers or less.

4. The method of claim 3, wherein the orientations of the respective crystal lattices are directionally aligned to each other by better than about 1 degree.

5. The method of claim 3, wherein the discrete seed structures of the array comprise ones of a plurality of discrete seed structures on the source substrate including respective crystal lattices having the substantially similar orientations, and wherein assembling the array comprises:

transferring the ones of the plurality of discrete seed structures from the source substrate to the surface of the target substrate while maintaining the substantially similar orientations of the respective crystal lattices thereof.

6. The method of claim 5, wherein transferring comprises transfer printing the ones of the plurality of discrete seed structures from the source substrate to the surface of the target substrate using an elastomer stamp.

7. The method of claim 5, wherein the plurality of the discrete seed structures comprise portions of a single-crystal seed layer grown on the source substrate.

8. The method of claim 3, wherein the selectively growing occurs laterally such that the respective semiconductor layers collectively define a continuous layer extending along the surface of the target substrate.

9. The method of claim 8, wherein the continuous layer is substantially monocrystalline.

10. The method of claim 9, wherein the target substrate is monocrystalline, polycrystalline, or amorphous.

11. The method of claim 8, wherein the continuous layer on the target substrate has a surface area of greater than about 100 square centimeters (cm²).

12. The method of claim 11, wherein the target substrate is larger than the source substrate.

13. The method of claim 3, wherein the respective semiconductor layers are eptiaxially grown on the seed structures on the target substrate without the use of metamorphic buffers.

14. The method of claim 3, wherein crystal lattices of the respective semiconductor layers have substantially similar lattice constants and have the substantially similar orientations as those of the discrete seed structures.

15. The Method of claim 14, wherein the source substrate has a different lattice constant than those of the discrete seed structures.

16. The method of claim 3, wherein a rate of growth of the respective semiconductor layers on the seed structures is greater than a rate of growth of the respective semiconductor layers on the surface of the target substrate.

17. The method of claim 16, wherein the target substrate includes a thin film on regions of the surface thereof between the discrete seed structures.

18. The method of claim 3, wherein the target substrate comprises silicon or an alloy thereof, aluminum or aluminum oxide, silicon dioxide, or molybdenum.

19. The method of claim 18, wherein the seed structures and the respective semiconductor layers epitaxially grown thereon comprise III-V materials, group IV materials, or II-VI materials.

20. An engineered substrate, comprising:

an array of discrete seed structures on a surface of a target substrate different than a source substrate thereof, the discrete seed structures comprising respective crystal lattices having substantially similar orientations.

21. The substrate of claim 20, wherein neighboring ones of the discrete seed structures on the surface of the target substrate are separated by about 10 micrometers or less, and wherein the orientations of the respective crystal lattices thereof are directionally aligned to each other by better than about 1 degree.