SEMICONDUCTOR PACKAGE ASSEMBLY

• US 20140264812A1
• Filed: 02/25/2014
• Published: 09/18/2014
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: CHANG, Sheng-Ming, HSIEH, Tung-Hsien, CHEN, Nan-Cheng
• Granted Patent: US 9,331,054 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/15183 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/1053 : Mounted components directly electrically connected to each other, i.e. not via the PCB

Abstract

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.

Claims

1. A semiconductor package assembly, comprising:

a first semiconductor package, comprising;

a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface; and

a second semiconductor package bonded to the first device-attach surface of the first semiconductor package, wherein the second package comprises;

a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface;

a dynamic random access memory (DRAM) device mounted on the second device-attach surface;

a decoupling capacitor mounted on the second device-attach surface; and

conductive structures disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.

2. The semiconductor package assembly as claimed in claim 1, wherein a boundary of the first body fully overlaps with a boundary of the second body in a top view.

3. The semiconductor package assembly as claimed in claim 1, wherein the first semiconductor package further comprises a logic device mounted on the first device-attach surface of the first body.

4. The semiconductor package assembly as claimed in claim 1, wherein the DRAM device and the decoupling capacitor are separated from each other.

5. The semiconductor package assembly as claimed in claim 3, further comprising:

a base, wherein the first and second semiconductor packages are mounted on the base through the conductive structures of the first semiconductor package; and

an external power supply disposed on the base, separated from the first and second semiconductor packages.

6. The semiconductor package assembly as claimed in claim 5, wherein the decoupling capacitor is coupled to both the logic device and the external power supply.

7. The semiconductor package assembly as claimed in claim 5, wherein the decoupling capacitor is coupled to the DRAM device, a DRAM controller integrated with the logic device and the external power supply.

8. The semiconductor package assembly as claimed in claim 1, wherein the DRAM device and the decoupling capacitor are coupled to the first semiconductor package through different conductive structures disposed on the second bump-attach surface.

9. The semiconductor package assembly as claimed in claim 1, wherein the second semiconductor package further comprises an additional DRAM device vertically stacked on the DRAM device, electrically coupled to the second body.

10. A dynamic random access memory (DRAM) package assembly, comprising:

a base;

a DRAM package bonded to the base, wherein the DRAM package comprises;

a body;

a DRAM device mounted on the body; and

a decoupling capacitor mounted on the body, separated from the DRAM device; and

an external power supply disposed on the base, separated from the DRAM package.

11. The semiconductor package assembly as claimed in claim 10, further comprising:

a logic package between the DRAM package and the base, comprising;

a body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface;

a logic device mounted on the first device-attach surface of the body; and

first conductive structures disposed on the first bump-attach surface, in contact with the base.

12. The semiconductor package assembly as claimed in claim 11, wherein the DRAM package bonded to and in contact with the first device-attach surface through second conductive structures disposed on a second bump-attach surface of the body of the DRAM package.

13. The semiconductor package assembly as claimed in claim 12, wherein the body of the DRAM package has a second device-attach surface opposite to the second bump-attach surface, and wherein the DRAM device is mounted on the second device-attach surface.

14. The semiconductor package assembly as claimed in claim 10, wherein a boundary of the body of the DRAM package is aligned to a boundary of the body of the logic package in a top view.

15. The semiconductor package assembly as claimed in claim 11, wherein the decoupling capacitor is coupled to both the logic device and the external power supply.

16. The semiconductor package assembly as claimed in claim 11, wherein the decoupling capacitor is coupled to the DRAM device, a DRAM controller integrated with the logic device and the external power supply.

17. The semiconductor package assembly as claimed in claim 12, wherein the DRAM device and the decoupling capacitor are coupled to the logic package through different conductive structures disposed on the second bump-attach surface.

18. The semiconductor package assembly as claimed in claim 10, wherein the DRAM package further comprises an additional DRAM device vertically stacked on the DRAM device, electrically coupled to the body of the DRAM package.

19. A semiconductor package assembly, comprising:

a base;

a system-on-chip (SOC) package bonded to the base;

a memory package bonded to the system-on-chip (SOC) package, wherein the memory package comprises a decoupling capacitor mounted thereon; and

an external power supply disposed on the base, separated from the system-on-chip (SOC) package.

20. The semiconductor package assembly as claimed in claim 19, wherein the system-on-chip (SOC) package comprises:

a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface;

a logic device mounted on the first device-attach surface; and

first conductive structures disposed on the first bump-attach surface, in contact with the base.

21. The semiconductor package assembly as claimed in claim 20, wherein the memory package is a dynamic random access memory (DRAM) package.

22. The semiconductor package assembly as claimed in claim 21, wherein the DRAM package comprises:

a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface;

a dynamic random access memory (DRAM) device and the decoupling capacitor mounted on the second device-attach surface; and

second conductive structures disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the system-on-chip (SOC) package.

23. The semiconductor package assembly as claimed in claim 22, wherein the DRAM device and the decoupling capacitor are discrete devices.

24. The semiconductor package assembly as claimed in claim 22, wherein a boundary of the second body of the DRAM package is aligned to a boundary of the first body of the system-on-chip (SOC) package in a top view.

25. The semiconductor package assembly as claimed in claim 20, wherein the decoupling capacitor is coupled to both the logic device and the external power supply.

26. The semiconductor package assembly as claimed in claim 22, wherein the decoupling capacitor is coupled to the DRAM device, a DRAM controller integrated with the logic device and the external power supply.

27. The semiconductor package assembly as claimed in claim 22, wherein the DRAM device and the decoupling capacitor are coupled to the system-on-chip (SOC) package through different conductive structures disposed on the second bump-attach surface.

28. The semiconductor package assembly as claimed in claim 22, wherein the DRAM package further comprises an additional DRAM device vertically stacked on the DRAM device, electrically coupled to the second body.